Displaying 20 results from an estimated 6000 matches similar to: "where is hypervisor''s kernel log? (xm dmesg just prints the ring buffer)"
2008 Feb 13
17
Xen 3.2 is not loading on FC8 - Error: Kernel panic - Attempted to kill init
Hi all,
I compiled and installed Xen 3.2 source on FC8. Compilation and installation
completed with no errors. However when I try to load Xen I get an error:
Kernel panic - Attempted to kill init !!!
This is my grub configuration:
# grub.conf generated by anaconda
#
# Note that you do not have to rerun grub after making changes to this file
# NOTICE: You have a /boot partition. This means
2008 Feb 15
4
Pin CPU of dom0
Hello,
I searched the mail list, but can''t find a solution.
I have a machine with 8 cores. I want to set the CPU affinity for dom0. For
example, let Dom0 use processor 0-3, let guests use 4-7
For guest domains, I can do this by setting the "cpus"
For dom0. there''s no such option. The only one I know is in /etc/xen-
config.sxp, which has "dom0-cpus" setting.
2012 Sep 24
0
[LLVMdev] Proposal: New DAG node type for reciprocal operation
Yes, what I mean is a target independent node in the ISD::NodeType enum.
I already did the node transformation DAGCombiner and target-specific lowering in the first place. It worked. But introducing a specific node will make the logic more clear.
For example, in ARM, FDIV is a scalar operation. So, after DAGCombiner and Vector Type legalize, vectorized FDIV has been expanded into scalar versions,
2012 Sep 21
2
[LLVMdev] Proposal: New DAG node type for reciprocal operation
--- On Thu, 9/20/12, Jim Grosbach <grosbach at apple.com> wrote:
From: Jim Grosbach <grosbach at apple.com>
Subject: Re: [LLVMdev] Proposal: New DAG node type for reciprocal operation
To: "Weiming Zhao" <weimingz at codeaurora.org>
Cc: llvmdev at cs.uiuc.edu
Date: Thursday, September 20, 2012, 3:32 PM
Sounds like a reasonable fit for a target-specific DAG combine. I
2014 Mar 12
3
[LLVMdev] [ARM] [PIC] optimizing the loading of hidden global variable
Hi,
When Im compiling a code with fvisibility=hidden fPIC for ARM, I find
that LLVM generates less optimized code than GCC.
For example:
test.cpp:
void init(void *);
int g0[100];
int g1[100];
int g2[100];
void foo() {
init(&g0);
init(&g1);
init(&g2);
}
Clang will emit 1 GOT entry for each GV and 2 instructions to get the
address:
ldr
2012 Sep 20
0
[LLVMdev] Proposal: New DAG node type for reciprocal operation
Sounds like a reasonable fit for a target-specific DAG combine. I suspect a target specific node wouldn't be necessary and the patterns could be matched directly.
-Jim
On Sep 20, 2012, at 3:26 PM, Weiming Zhao <weimingz at codeaurora.org> wrote:
> Hi,
>
> In relaxed/fast math mode, if we can convert a/b to a * (1/b), we may get more performance when (1) “b” is loop
2017 Apr 05
2
compiler-rt, v4.0: arm\udivsi3.S broken for division by zero
Yes, it's a bug.
Please review https://reviews.llvm.org/D31716
On 4/5/2017 3:50 AM, Renato Golin wrote:
> On 21 March 2017 at 18:32, Peter Jakubek via llvm-dev
> <llvm-dev at lists.llvm.org> wrote:
>> I think the current implementation for the call "bl __aeabi_idiv0" in
>> builtins\arm\udivsi3.S is broken.
>> At least for the case that __aeabi_idiv0
2014 Jun 20
2
[LLVMdev] [AArch64] Question about far call
Hi,
For the following code:
void foo ();
int main () {foo();}
llvm emits "bl foo"
Then I set foo at a far address in linking:
aarch64-linux-gnu-gcc -Wl,--defsym=foo=0x80000000 a.o -o a.exe
I got an error from ld:
a.c:(.text+0x8): relocation truncated to fit: R_AARCH64_CALL26 against
symbol `foo' define in *ABS* section in a.exe
The question is: do I
2014 Mar 14
2
[LLVMdev] [ARM] [PIC] optimizing the loading of hidden global variable
Hi Rafael,
Yes, merging gv prevents linker to do garbage collection. Should it be implemented as a peephole pass? If we do it too early, the distance between GVs are not fixed yet.
PS:
Below is the GCC output with "extern" hidden:
ldr r2, .L2
stmfd sp!, {r3, lr}
.save {r3, lr}
.LPIC0:
add r0, pc, r2
bl _Z4initPv(PLT)
ldr r1, .L2+4
.LPIC1:
add r0, pc, r1
bl _Z4initPv(PLT)
ldr
2012 Oct 27
3
how to save xm dmesg into a file
Hi,all,
the dmesg have a ring buffer size that is only 16k, so when overflows, some
of the printk() messages get lost. SO could someone please give me a
solution how to save all log message to a file. I don''t have serial port
and cannot use that method to save log on another machine. Thanks!
_______________________________________________
Xen-users mailing list
Xen-users@lists.xen.org
2012 Sep 20
2
[LLVMdev] Proposal: New DAG node type for reciprocal operation
Hi,
In relaxed/fast math mode, if we can convert a/b to a * (1/b), we may get
more performance when (1) "b" is loop invariant or (2) arch has faster
reciprocal instruction (e.g. recipe/recips on ARM) or (3) arch has no
vector div, but has vector mul and recip.
So ,with this node type, a div node can be converted to a mul and a recip
when desired. Then, each arch can further
2016 Mar 17
2
How to let LLVM handle undefined behavior more gracefully?
Hi,
There are cases where LLVM is able to detect some UB but clang is not.
For example,
unsigned int foo(unsigned int x) {
int ret = 0;
for(int i = 0; i <= 32; ++i)
ret += x >> i;
return ret;
}
When the loop is unrolled, LLVM InstructionSimplify will catch it and
return a UNDEF value.
How can we let LLVM report some warning message to help developers
correct the error?
2015 Dec 08
2
weak definitions in LTO
Hi,
I have a question regarding the behavior of weak symbol resolution in LTO:
Suppose there are weak definitions in both the source code and some
native lib.
In non-LTO path, we will use the version from source code.
In LTO path, LLVM may discard the definition as it has "linkeonce"
linkage type. So the native version will be selected by linker.
Now, non-LTO and LTO build may have
2009 Mar 25
1
"xm dmesg" ring buffer size option?
I have a large system with pretty voluminous boot time messages that
are exceeding the capacity of the ring buffer displayed by "xm dmesg"
(i.e., the early messages are lost, and I see only the last messages).
With a regular, non-Xen kernel, I use "log_buf_len=size" to enlarge the
printk ring buffer size, but this boot option doesn''t seem to work
for Xen.
Anyone have
2008 Jun 09
3
xm balloon - Command balloon is deprecated
I tryed te baloon out a domu and get:
xm balloon VS01 1
Command balloon is deprecated
But i need it... What can i doo?
Dom0: Debian Etch - Kernel 2.6.18-6-xen-686
DomU: Debian Etch - 2.6.18-6-xen-vserver-686
_______________________________________________
Xen-users mailing list
Xen-users@lists.xensource.com
http://lists.xensource.com/xen-users
2008 Mar 11
3
Is it possible to make hypercall from user application directly?
Hi,
I implemented my own Hypercall in xen.
Now I wish my application under dom0 could talk to Xen via my hypercall.
Currently, I make a stub in dom0''s kernel, which works as a proxy to forward
the request. So, my application first makes a system call to dom0, which
then makes hypercall to xen.
Is this design necessary? May I call hypercalls from user application under
dom0 directly?
2016 Apr 16
2
[cfe-dev] [libunwind] __ELF__ macro for arm-none-eabi
On 16 April 2016 at 01:44, Zhao, Weiming via cfe-dev
<cfe-dev at lists.llvm.org> wrote:
> I'm building libunwind for ARM baremetal using clang.
> I notice that __ELF__ is used in libunwind and the macro is only defined for
> Linux target on ARM.
> Should we also predefine that for arm-none-eabi target?
Do you mean in Clang's ARMTargetInfo::getTargetDefines() ?
I think
2013 Mar 13
0
[LLVMdev] Problems with 64-bit register operands of inline asm on ARM
On Mar 13, 2013, at 10:15 AM, Weiming Zhao <weimingz at codeaurora.org> wrote:
> Hi Renato,
>
> It seems to me that LLVM doesn’t parse the inline asm body. It just checks the constraints, (ie. Input/output interface). During ASM writing, it then binding those constraints to placeholders like %0, %1.
This is correct.
> So it a constraint is a 64-integer type, it *probably*
2013 Mar 13
3
[LLVMdev] Problems with 64-bit register operands of inline asm on ARM
Hi Renato,
It seems to me that LLVM doesnt parse the inline asm body. It just checks
the constraints, (ie. Input/output interface). During ASM writing, it then
binding those constraints to placeholders like %0, %1.
So it a constraint is a 64-integer type, it *probably* needs paired GPR.
Weiming
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by
The
2009 Aug 25
1
unknown connection
Hello,
Today I updated one of our computers running CentOS 5.3 32bit. After a
reboot I notice the following with lsof -i
sshd 3638 root 3u IPv6 17317 TCP
pc46.astro.up.pt:ssh->119.1.193.205:zephyr-clt (ESTABLISHED)
sshd 3639 sshd 3u IPv6 17317 TCP
pc46.astro.up.pt:ssh->119.1.193.205:zephyr-clt (ESTABLISHED)
What is this connection?