similar to: [PATCH] MTRR MSRs Save/Restore

IF guest CR0.wp is 0 and the destination address is ReadOnly, we have to emulate it. Reviewed-by: Kevin Tian <kevin.tian@intel.com> Signed-off-by: Disheng Su <disheng.su.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

The first and third patches are cleaned up versions of an earlier v3 submission by Yang. 1: Nested VMX: check VMX capability before read VMX related MSRs 2: VMX: clean up capability checks 3: Nested VMX: fix IA32_VMX_CR4_FIXED1 msr emulation 4: x86: make hvm_cpuid() tolerate NULL pointers Signed-off-by: Jan Beulich <jbeulich@suse.com>

The attached patch fixes the save/restore issue seen with 32bit Windows guest VMs. The root cause is that current Xen doesn''t intercept SYSENTER-related MSRs for 32bit guest VMs. As a result, the guest_sysenter_xxx fields contain incorrect values and shouldn''t be used for save/restore. This patch checks the LMA bit of EFER register in the save/restore code path. Please apply it

Hello, I recently tried Xen 3.0.3-testing on my 2x Opteron-244 SMP machine. Everything works well exept one detail, which is not unimportant to me: the powernow-k8 driver fails to switch frequencies. A closer look on the powernow-k8 source reveals, that some MSR write operations seem to be without any effect. A rdmsr() before and after the wrmsr() call reveals that no real change on the register

Hi, I'm running libvert on a Debian 7 system. I have upgraded libvert and qemu from source (v1.06 and 1.5.0 respectively) and the problem persists. The guest OS is also a Debian 7 system running a non-SMP kernel. The error message from virt-manager is Error starting domain: unsupported configuration: guest and host CPU are not compatible: Host CPU does not provide required features: rtm,

On 06/13/2013 10:11 PM, Michael Giardino wrote: > Hi, > > I'm running libvert on a Debian 7 system. I have upgraded libvert and qemu > from source (v1.06 and 1.5.0 respectively) and the problem persists. The > guest OS is also a Debian 7 system running a non-SMP kernel. The error > message from virt-manager is > > Error starting domain: unsupported configuration:

Hello, I''m trying to use the VT technology on box but when I start Xen VMX is disabled by Feature Control MSR as shown in the following message: Xen version 3.0.2-3 (guill@frec.bull.fr) (gcc version 3.3.5 (Debian 1:3.3.5-13)) Wed May 31 16:07:00 CEST 2006 Latest ChangeSet: Tue May 30 18:14:05 2006 +0100 9697:18e8e613deb9 ... (XEN) Initializing CPU#0 (XEN) Detected 3391.682 MHz

On Sun, Jun 03, 2012 at 05:31:32PM +1000, aorchis@gmail.com wrote: > Hi Jeremy and Konrad, CC-ing xen-devel. > > Basically the driver NVIDIA provided is a binary blob and recent > versions does not work with the PAT layout of XEN so it falls back to > MTRR to provide write combining (please correct me if I''m wrong). OK? Which is still OK. Are you using a v3.4 kernel

Hi, while testing some APERF/MPERF semantics I discovered that this feature is enabled in Xen Dom0, but is not reliable. The Linux kernel''s scheduler uses this feature if it sees the CPUID bit, leading to costly RDMSR traps (a few 100,000s during a kernel compile) and bogus values due to VCPU migration during the measurement. The attached patch explicitly disables this CPU capability

The patch attached is to set effective memory type for EPT according to the VT-d snoop control capability, and also includes some cleansup for EPT & VT-d both enabled. Signed-off-by: Zhai, Edwin Edwin.Zhai@intel.com<mailto:Edwin.Zhai@intel.com> Signed-off-by: Xin, Xiaohui xiaohui.xin@intel.com<mailto:xiaohui.xin@intel.com> _______________________________________________

To avoid MSR save/restore at every VM exit/entry time, we restore the x86_64 specific MSRs at domain switch time if modified. In VMX domains, we modify those upon requests from the guests to that end. Note that IA32_EFER.LME and IA32_EFER.LMA are saved/restored by H/W on every VM exit. For the usual domains (i.e. dom0 and domU), those MSRs are not modified once set at initialization time, so we

Implement AMD MSRs for vMCE Signed-off-by: Christoph Egger <Christoph.Egger@amd.com> -- ---to satisfy European Law for business letters: Advanced Micro Devices GmbH Einsteinring 24, 85689 Dornach b. Muenchen Geschaeftsfuehrer: Alberto Bozzo Sitz: Dornach, Gemeinde Aschheim, Landkreis Muenchen Registergericht Muenchen, HRB Nr. 43632 _______________________________________________

Propagate guest MSR writes to machine MSRs immediately Right now, we have an exposure between the time the MSR is written and used by an instruction such as syscall. If there is a context switch and we do vmx_do_restore_msrs(), everything goes fine. But if we don''t, then we execute the syscall with the wrong MSR. Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>

Allow AMD MSRs injected via xen-mceinj Signed-off-by: Christoph Egger <Christoph.Egger@amd.com> -- ---to satisfy European Law for business letters: Advanced Micro Devices GmbH Einsteinring 24, 85689 Dornach b. Muenchen Geschaeftsfuehrer: Alberto Bozzo Sitz: Dornach, Gemeinde Aschheim, Landkreis Muenchen Registergericht Muenchen, HRB Nr. 43632

On Thu, Sep 18, 2014 at 9:36 AM, KY Srinivasan <kys at microsoft.com> wrote: > > I am copying other Hyper-V engineers to this discussion. > Thanks, K.Y. In terms of the address for the MSR, I suggest that you choose one from the range between 40000000H - 400000FFH. The SDM (35.1 ARCHITECTURAL MSRS) says "All existing and future processors will not implement any features using

On Thu, Sep 18, 2014 at 9:36 AM, KY Srinivasan <kys at microsoft.com> wrote: > > I am copying other Hyper-V engineers to this discussion. > Thanks, K.Y. In terms of the address for the MSR, I suggest that you choose one from the range between 40000000H - 400000FFH. The SDM (35.1 ARCHITECTURAL MSRS) says "All existing and future processors will not implement any features using

Hi, http://xenbits.xensource.com/xen-unstable.hg?rev/aab9fbd6ffa0 from http://lists.xensource.com/archives/html/xen-devel/2008-07/msg00518.html restricts the CPUID masking feature to model 0x1d or model 0x17 with stepping >=4: if (!((model == 0x1d) || ((model == 0x17) && ((eax & 0xf) >= 4)))) { /* fail ... */ A Xeon E5520 which is supposed to

[PATCH] Clean up x86 control register and MSR macros This patch is based on Rusty's recent cleanup of the EFLAGS-related macros; it extends the same kind of cleanup to control registers and MSRs. It also unifies these between i386 and x86-64; at least with regards to MSRs, the two had definitely gotten out of sync. Signed-off-by: H. Peter Anvin <hpa@zytor.com> diff -urN

[PATCH] Clean up x86 control register and MSR macros This patch is based on Rusty's recent cleanup of the EFLAGS-related macros; it extends the same kind of cleanup to control registers and MSRs. It also unifies these between i386 and x86-64; at least with regards to MSRs, the two had definitely gotten out of sync. Signed-off-by: H. Peter Anvin <hpa@zytor.com> diff -urN

Could anyone summarize what the support status of cpu frequency changes is at present. I don''t seem to recall generic changes to the hpyervisor in that respect, but the linux tree has fairly extensive changes to the powernow-k8 driver (which would make sense to me only if all other cpufreq drivers are fully supported now, too). Thanks, Jan