similar to: [PATCH] remove unused nopaging_gdt_descr

Sorry, forget to join lists. Regards, Jinsong -----Original Message----- From: Liu, Jinsong Sent: 2007年5月16日 8:23 To: ''Keir Fraser''; Tian, Kevin; xen-devel@lists.xensource.com Subject: RE: [Xen-devel] trap/interrupt gate for hypercall In native linux, syscall (gate type 15) and its RESTORE_ALL code provides weak fixup mechanism when reload segment register, by sending 0

F.Y.I >>> "Tian, Kevin" <kevin.tian@intel.com> 08.11.27. 11:50 >>>Sorry for a typo. I did mean domU instead of dom0. :-) The point here is that time_resume will sync to new system time and wall clock at restore, and thus pv guest should be able to continue... Xen system time is not wallclock time which just counts up from power up. As Keir points out, only its

Just found this patch in house which I thought sent out already. :-) Still one thing remaining is to special case for UP guest which suffers overhead from this change... ---- Remove lock on first guest table walk Existing shadow fault path grabs big lock before walking guest tables, to ensure consistency with shadow content lest concurrent change from other vcpu in a bad OS. But this lock

Hi, Keir, Attached are the necessary changes in control panel to support ia64/vti domain builder. One is in common side, and the other is in vti specific image builder. Please take a look, and if no objection, I''d like to ask Dan''s help to check into xen-ia64-unstable.hg first. Signed-off-by Ke Yu <ke.yu@intel.com> Signed-off-by Anthony Xu <anthony.xu@intel.com>

Is there any trouble with mailing list? I didn''t see my mail sent back after almost 8hrs. :-( Thanks, Kevin -----Original Message----- From: Tian, Kevin Sent: 2008年2月22日 10:33 To: ''Tim Deegan'' Cc: xen-devel@lists.xensource.com Subject: [PATCH][UPDATE]Remove lock on guest table walk >From: Tim Deegan >Sent: 2008年2月21日 22:13 >Hi, > >So, the idea seems

This patch adds lost logic for vga initialization. It was lost after changing to new Qemu. Signed-off-by : Kevin Tian <kevin.tian@intel.com> Signed-off-by : Zhang Xiantao <xiantao.zhang@intel.com> Thanks & Best Regards -Xiantao OTC,Intel Corporation _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com

flight 8803 xen-unstable real [real] http://www.chiark.greenend.org.uk/~xensrcts/logs/8803/ Regressions :-( Tests which did not succeed and are blocking: test-amd64-i386-rhel6hvm-intel 4 xen-install fail REGR. vs. 8769 test-amd64-i386-xl 4 xen-install fail REGR. vs. 8769 test-amd64-i386-pair 6 xen-install/dst_host fail REGR. vs. 8769

Signed-off-by Kevin Tian <kevin.tian@intel.com> Thanks, Kevin _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

Yes, like real Linux/ia64, it is not possible to run the same Xenlinux bits both on ski and on real hardware. A different configuration and build is required. The config difference is the same as it was with the privified xenlinux... I think you did that successfully before (with privified xenlinux) so give that config file a try and if it doesn''t work, let me know. BTW, I think I know

IF guest CR0.wp is 0 and the destination address is ReadOnly, we have to emulate it. Reviewed-by: Kevin Tian <kevin.tian@intel.com> Signed-off-by: Disheng Su <disheng.su.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

Simplify paging_invlpg when flush is not required. New ''flush'' parameter is added to paging_invlpg, to allow caller assigning whether flush check is required. It''s wasteful to always validate shadow linear mapping if caller doesn''t check return value at all. Signed-off-by Kevin Tian <kevin.tian@intel.com> Thanks, Kevin

Clean up time.c Signed-off-by Guanqun Lu <guanqun.lu@intel.com> Signed-off-by Kevin Tian <kevin.tian@intel.com> Thanks, Kevin _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

One more fix about PMR disable. Move PMR disable into per-iommu enable function, instead of in current iommu_setup which only takes effect on first VT-d engine. This change also enlightens S3 resume path. Signed-off-by Gang Wei (Jimmy) <gang.wei@intel.com> Signed-off-by Kevin Tian <kevin.tian@intel.com> Thanks, Kevin _______________________________________________ Xen-devel

I assume this commit message was supposed to be "Enable VGA acceleration for VTI" right? We''re not actually accelerating CGA right? Regards, Anthony Liguori Xen patchbot-unstable wrote: > # HG changeset patch > # User kaf24@firebug.cl.cam.ac.uk > # Node ID e67432187b88ee60433779ad0f004b532ed378c8 > # Parent 639ad22eb7c80ac21c3958747b879892680bdaba >

Dom0 doesn''t need to save/restore ioapic state across S3 suspend/resume, as Xen already does it. The more important is to avoid warnings on some platforms which may have uninitialized RTEs to be weird value (like smi mode) but masked. When dom0 saves those entries and then write back later, it''s easy to trigger Xen''s sanity check from ioapic_guest_write. Signed-off-by

Add TSC stop support for Deep C state TSC may stop at deep C state (C3/C4...) entry/exit. this patch add the logic that save and restore TSC during deep C state entry/exit, by using platform timer (PIT/HPET) signed-off-by: Yu Ke <ke.yu@intel.com> signed-off-by: Tian Kevin <kevin.tian@intel.com> signed-off-by: Wei Gang<gang.wei@intel.com>

Local APIC timer may stop at deep C state (C3/C4...) entry/exit. Initial HPET broadcast working in legacy replacing mode, broke RTC intr, so was bypassed. This patch add the logic that use platform timer (PIT) to reenable local APIC timer at C state entry/exit. Currently, only keep PIT enabled with 100Hz freq. The next step is trying to dynamically enable/disable PIT while needed, and give it

Hi, Keir, Attached patch is the qemu part to enable VGA acceleration for VTI domain. It also fixes a small point about increasing maximum mem for the new linear buffer. Signed-off-by Kevin Tian <kevin.tian@intel.com> Thanks, Kevin _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

HPET intr-near-missing means if the current counter value is too close to the comparator value to be reprogrammed the expected HPET intr may be missing. Linux kernel uses a mininal 48-hpet-ticks(~3.5us) distance to workaround this, but personal observation showed there is still failure case while delta=0xba (~13.5us). So choosing 20us as the MIN_DELTA_NS should be helpful to prevent near-missing

The patch removes the duplicate spin_lock_irqsave to spin_lock in the Vt-d code path. The duplicate spin_lock_irqsave() flushes the original EFLAGS saved, and thus disable the local irq. Signed-off-by: Xin, Xiaohui Xiaohui.xin@intel.com Signed-off-by: Tian, Kevin <Kevin.Tian@intel.com> _______________________________________________ Xen-devel mailing list