Displaying 20 results from an estimated 5000 matches similar to: "quick pointers needed"
2010 Jan 14
1
lattice dotplot with missing levels in factor variable
Hi,
I am trying to create a dotplot where each panel shows levels vs.
responses; the levels are sorted by responses but levels vary from one
panel to another. However, I run into problems with controlling the
y-limits and y-labels.
In particular, suppose I have a data frame
rsp <- c(10,2,4,0,2,3)
lvl <-
2008 Dec 28
2
zfs mount hangs
Hi,
System: Netra 1405, 4x450Mhz, 4GB RAM and 2x146GB (root pool) and
2x146GB (space pool). snv_98.
After a panic the system hangs on boot and manual attempts to mount
(at least) one dataset in single user mode, hangs.
The Panic:
Dec 27 04:42:11 base ^Mpanic[cpu0]/thread=300021c1a20:
Dec 27 04:42:11 base unix: [ID 521688 kern.notice] [AFT1] errID
0x00167f73.1c737868 UE Error(s)
Dec 27
2013 Nov 06
2
[LLVMdev] loop vectorizer: Unexpected extract/insertelement
The following IR implements the following nested loop:
for (int i = start ; i < end ; ++i )
for (int p = 0 ; p < 4 ; ++p )
a[i*4+p] = b[i*4+p] + c[i*4+p];
define void @main(i64 %arg0, i64 %arg1, i1 %arg2, i64 %arg3, float*
noalias %arg4, float* noalias %arg5, float* noalias %arg6) {
entrypoint:
br i1 %arg2, label %L0, label %L1
L0:
2013 Nov 06
0
[LLVMdev] loop vectorizer: Unexpected extract/insertelement
The loop vectorizer relies on cleanup passes to be run after it:
from Transforms/IPO/PassManagerBuilder.cpp:
// Add the various vectorization passes and relevant cleanup passes for
// them since we are no longer in the middle of the main scalar pipeline.
MPM.add(createLoopVectorizePass(DisableUnrollLoops));
MPM.add(createInstructionCombiningPass());
2007 Jun 16
5
zpool mirror faulted
I have a strange problem with a faulted zpool (two way mirror):
[root at einstein;0]~# zpool status poolm
pool: poolm
state: FAULTED
scrub: none requested
config:
NAME STATE READ WRITE CKSUM
poolm UNAVAIL 0 0 0 insufficient replicas
mirror UNAVAIL 0 0 0 corrupted data
c2t0d0s0 ONLINE 0
2013 Nov 06
2
[LLVMdev] loop vectorizer: Unexpected extract/insertelement
The instcombine pass cleans up a lot.
Any idea why there are still shufflevector, insertelement, *and* bitcast
(!!) etc. instructions left? The original loop is so clean, a textbook
example I'd say. There is no need to shuffle anything.At least I don't
see it.
Frank
vector.ph: ; preds = %L5
%broadcast.splatinsert1 = insertelement <4 x
2008 Nov 13
5
BAD TRAP with Crossbow Beta October 31 2008
Hi.
I tried to send this to the mailing list, but it never showed up in the
archives, so I''m trying the forum instead...
I recently installed the Crossbow Beta October 31 2008 on my
SunFire T1000, and let me first say that I''m very pleased
with the functionality it provides.
What''s not so pleasing is the fact that after installing this,
the computer now get very
2004 Oct 17
3
question about Rcmd SHLIB
Dear R-people:
I tried to create a shared library in Windows XP. However I got error
messages which attached below:
C:\lasso>Rcmd SHLIB all.f cox.f
gcc all.o libR makeMakedeps all.dll -o all
gcc.exe: libR: No such file or directory
gcc.exe: makeMakedeps: No such file or directory
make: *** [all] Error 1
I have created shard libraries successfully before. Also for the same
fortran files:
2010 Aug 02
2
[LLVMdev] indirectbr and phi instructions
Hi,
How does the requirement that phi instructions have one value per
predecessor basic block interact with indirectbr instructions? For
instance, take the following code:
L1:
br i1 %somevalue, label %L2, label %L3
L2:
%ret1 = i8* blockaddress(@myfunction, %L5)
br label %L4
L3:
%ret2 = i8* blockaddress(@myfunction, %L6)
br label %L4
L4:
%ret = phi i8* [%ret1, L2], [%ret2, L3]
2018 Mar 10
2
NHW Project - lower quality settings
Hi David!
Many thanks for your very encouraging and kind feedback!!! (Hope you don't
mind that I made your post public on the Theora channel).
I try to be the more sincere as I can in my posts.Some people suggested me
to make demo pages to explain how the codec works step by step, and I
realize that it would be good, because certainly it will show that the NHW
codec is not that complex and
2013 Nov 01
2
[LLVMdev] loop vectorizer: this loop is not worth vectorizing
I am trying a setup where the one loop is rewritten as two loops. This
avoids the 'rem' and 'div' instructions in the index calculation (which
give the loop vectorizer a hard time).
However, with this setup the loop vectorizer complains about a too small
loop.
LV: Checking a loop in "main"
LV: Found a loop: L3
LV: Found a loop with a very small trip count. This loop
2012 Sep 25
2
Strange data frame behavior
Hello all,
I don't understand a strange behavior in data frame manipulation.
data_frame1 = data.frame(Site = c("S1", "S2", "S3", "S4", "L1", "L2",
"L3", "L4"),
Number = c(1, 3, 5, 2, 1, 1, 2, 1))
data_frame2 = data_frame1 [data_frame1$Site != "S1", ]
dput (data_frame2)
structure(list(Site =
2013 Nov 01
0
[LLVMdev] loop vectorizer: this loop is not worth vectorizing
In the case when coming from C it was probably the loop unroller and SLP
vectorizer which vectorized the code. Potentially I could do the same in
the IR. However, the loop body that is generated in the IR can get very
large. Thus, the loop unroller will refuse to unroll the loop in a large
number of (important) cases.
Isn't there a way to convince the loop vectorizer that it should
2018 Feb 18
1
NHW Project - high compression -l4 setting
Hello,
For those interested, I have added a -l4 high compression setting to the
NHW codec ( http://nhwcodec.blogspot.com/ ).This setting is very
experimental, I have boosted the sharpness for this one, but it can lack of
precision on low contrast areas.
This setting still maintains a good neatness and when it will be validated,
I will then make a new 0.1.4 version for the NHW Project.
High
2008 Sep 27
2
[LLVMdev] compile linux kernel
I plan to use virtualization infrastructure to JIT VM Kernel Code.
Michael Engel has done that in the past to have dynamic aspect in the
Kernel: http://llvm.org/pubs/2005-03-14-ACP4IS-AspectsKernel.pdf
He used L4 based Hypervisor and Virtual Machines. Can this not be done
or am I missing something?
-Ashish
On Sat, Sep 27, 2008 at 3:13 AM, Török Edwin <edwintorok at gmail.com> wrote:
>
2012 Jun 27
1
Strucchange: Breakpoint slow
Hi to all,
I am trying to run breakpoints() on a fairly large sample (>10.000
observations). The process is very slow, any idea on how to speed this up? I
have tried the hpc="foreach" parameter, but this didn't work at all when I
tried to run it on a smaller sample.
breakpoints(x ~ x.l1 + x.l2 + X.l3 + x.l4 + x.l5 + x.l6 + x.l7 + x.l8 + y.l1
+ y.l2 + y.l3 + y.l4 + y.l5 + y.l6
2018 Apr 16
1
NHW Project - quality improvement for -l4,-l5 settings
Hello,
I have improved quality for -l4 and -l5 high compression settings.These
settings are now really better and very competitive, I now prefer them
compared to x265 (HEVC).
Update at: http://nhwcodec.blogspot.com/
I am also working on -l6 quality setting, I can simply increase
quantization for it but I am not totally satisfied with this solution for
now... Looking for more advanced processing
2008 Mar 20
7
ZFS panics solaris while switching a volume to read-only
Hi,
I just found out that ZFS triggers a kernel-panic while switching a mounted volume
into read-only mode:
The system is attached to a Symmetrix, all zfs-io goes through Powerpath:
I ran some io-intensive stuff on /tank/foo and switched the device into
read-only mode at the same time (symrdf -g bar failover -establish).
ZFS went ''bam'' and triggered a Panic:
WARNING: /pci at
2008 Sep 27
0
[LLVMdev] compile linux kernel
On 2008-09-27 18:29, Ashish Bijlani wrote:
> I plan to use virtualization infrastructure to JIT VM Kernel Code.
> Michael Engel has done that in the past to have dynamic aspect in the
> Kernel: http://llvm.org/pubs/2005-03-14-ACP4IS-AspectsKernel.pdf
>
> He used L4 based Hypervisor and Virtual Machines. Can this not be done
> or am I missing something?
>
I think you'll
2016 Oct 12
2
Generate Register Indirect mode instruction
On 10/12/2016 3:15 PM, Alex Bradley wrote:
>
> Yes the result goes into memory. But the *address* of that destination
> memory location also needs to be loaded first into a register.
>
Your architecture has a single instruction for the following operation?
define void @foo(i32 **%a, i32**%b) {
entry:
%l1 = load i32*, i32** %a, align 4
%l2 = load i32, i32* %l1, align 4
%l3 =