similar to: R-beta: New R package for survival analysis

Displaying 20 results from an estimated 4000 matches similar to: "R-beta: New R package for survival analysis"

2004 Nov 14
2
Rcmd check for Windows fails (PR#7369)
Full_Name: Harald Weedon-Fekj?r Version: 2.0 OS: Windows Submission from: (NULL) (80.202.87.143) Dear R core Thanks again for a superb program. This is really one of the rare instances I find a bug. The bug is easy to bypass, but can be quite confusing; "Rcmd check" seems to fail without any good error report if the package contains a certain amount of R code and is run from a
2001 Mar 08
2
Smal problem with porting code to S-PLUS (PR#871)
Full_Name: Harald Fekjær Version: 1.22 OS: Windows Submission from: (NULL) (158.36.132.220) Dear R developers Actually, this is not a bug, but a small remark about a way R is working that makes trouble in porting the code to S. If I run the following i R: --- midl <- 4 attr(midl,"Object created") <- date() dump("midl","midl.R") --- I get a file like: ---
1997 Aug 25
0
R-alpha: R FAQ
Attached is a snapshot of the new version of the FAQ. What is still missing is something on eval and .Options versus options(). As always, feedback is greatly appreciated. Best, -k *********************************************************************** R FAQ Kurt Hornik v0.2-0, 1997/09/01 This document contains answers to some of the most frequently asked questions about R. Feedback
2008 Feb 18
1
can we include nonparametric component for survival regression?
i am trying to fit a survival regression model (cox model or parametric model) in R by including the covariate effects as a function m(x) instead of just beta*x. is it possible to fit such a model? can someone recommend some reference? I searched but only found a package called addreg where the hazard is actually modeled additively. That is not what i want. [[alternative HTML version deleted]]
2012 Apr 16
2
Problems with subset, droplevels and lm: variable lengths differ
[Env: R 2.14.2 / Win Xp] In the script below, I want to select some variables from rrcov::OsloTransect, delete cases with any missing data, and subset the data frame Oslo to remove cases for two levels of the factor litho that occur with low frequency. The checks I run on my new data frame Oslo look OK, but I when I try to fit a multivariate linear model with lm(), I am getting an error:
2016 Apr 27
2
[Sparc] builtin setjmp / longjmp - need help to get past last problem
Hi, I'm implementing __builtin_setjmp and __builtin_longjmp for Sparc 32 bit processors (64 bit later, time allowing). I'm basing the code on the PowerPC version, which itself is based on the X86 version. This code is very nearly working, and I've had it working for -O0 optimisation (with a slightly different version to that below), so I know it's close. However, the PowerPC
2008 Jul 02
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Evan Cheng wrote: > You need to insert new basic blocks and update CFG to accomplish this. > There is a hackish way to do this right now. Add a pseudo instruction > to represent this operation and mark it usesCustomDAGSchedInserter. > This means the intrinsic is mapped to a single (pseudo) node. But it > is then expanded into instructions that can span multiple basic >
2008 Jul 04
0
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Hi Gary, The patch looks great. But I do have one comment: +let usesCustomDAGSchedInserter = 1 in { + let Uses = [CR0] in { + let Uses = [R0] in + def ATOMIC_LOAD_ADD_I32 : Pseudo< The "let Uses = [R0]" is not needed. The pseudo instruction will be expanded like this later: + BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) +
2008 Jul 11
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Hi Evan, Evan Cheng wrote: > This does not patch cleanly for me (PPCISelLowering.cpp). Can you > prepare a updated patch? This should work, though I won't have access to my test box now until next Thursday so no guarantees :) Cheers, Gary -- http://gbenson.net/ -------------- next part -------------- Index: lib/Target/PowerPC/PPCISelLowering.h
1997 Dec 09
3
R-beta: R FAQ v0.60
An updated version of the R FAQ to accompany the new 0.60 release is now available at the usual site, http://www.ci.tuwien.ac.at/~hornik/R/R-FAQ.html A plain text version of the FAQ is appended below. -kh ****** snip snip snip ************************************************** R FAQ Kurt Hornik v0.60-6, 1997/12/08 This document contains answers to some of the most frequently asked
1997 Dec 09
3
R-beta: R FAQ v0.60
An updated version of the R FAQ to accompany the new 0.60 release is now available at the usual site, http://www.ci.tuwien.ac.at/~hornik/R/R-FAQ.html A plain text version of the FAQ is appended below. -kh ****** snip snip snip ************************************************** R FAQ Kurt Hornik v0.60-6, 1997/12/08 This document contains answers to some of the most frequently asked
1997 Dec 09
3
R-beta: R FAQ v0.60
An updated version of the R FAQ to accompany the new 0.60 release is now available at the usual site, http://www.ci.tuwien.ac.at/~hornik/R/R-FAQ.html A plain text version of the FAQ is appended below. -kh ****** snip snip snip ************************************************** R FAQ Kurt Hornik v0.60-6, 1997/12/08 This document contains answers to some of the most frequently asked
2008 Jul 09
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Ah, didn't see that, that's what comes of trying to do something at 5pm :) I attached an updated patch which creates a virtual register instead of using R0. How does this look? Cheers, Gary Dan Gohman wrote: > PPCTargetLowering::EmitInstrWithCustomInserter has a reference > to the current MachineFunction for other purposes. Can you use > MachineFunction::getRegInfo instead?
2008 Jul 08
0
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Look for createVirtualRegister. These are examples in PPCISelLowering.cpp. Evan On Jul 8, 2008, at 8:24 AM, Gary Benson wrote: > Hi Evan, > > Evan Cheng wrote: >> The patch looks great. But I do have one comment: >> >> +let usesCustomDAGSchedInserter = 1 in { >> + let Uses = [CR0] in { >> + let Uses = [R0] in >> + def ATOMIC_LOAD_ADD_I32 :
2008 Jul 08
3
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Hi Evan, Evan Cheng wrote: > The patch looks great. But I do have one comment: > > +let usesCustomDAGSchedInserter = 1 in { > + let Uses = [CR0] in { > + let Uses = [R0] in > + def ATOMIC_LOAD_ADD_I32 : Pseudo< > > The "let Uses = [R0]" is not needed. The pseudo instruction will be > expanded like this later: > > + BuildMI(BB,
2004 Sep 08
1
Feil i websider (PR#7216)
Warnings about /metno/internweb/fouweb/htdocs/teknisk/verktoy/R/faq.html BAD LINK: http://stat.ethz.ch/R/manual/ BAD LINK: http://nlme.stat.wisc.edu/MEMSS/ BAD LINK: http://stats.mth.uea.ac.uk/Rcgi/ BAD LINK: http://software.biostat.washington.edu/statsoft/ess/ ------------------------------------------------------------ Warnings about
2009 May 13
0
[LLVMdev] RFC: Code Gen Change!
On 13/05/2009, at 02.46, Bill Wendling wrote: > Instead of all of the booleans, you pass in a flag that has bits set > to indicate what state the register is in: > > namespace RegState { > enum { > Define = 0x1, > Implicit = 0x2, > Kill = 0x4, > Dead = 0x8, > EarlyClobber = 0x10, > ImplicitDefine = Implicit |
2009 May 13
2
[LLVMdev] RFC: Code Gen Change!
I just finished coding up a change to how code generation builds machine instructions. The change is in include/llvm/CodeGen/MachineInstrBuilder.h, where when you want to add a register, you have to specify a long list of booleans indicating if it's defined, implicit, killed, dead, or early clobbered. I don't know about you, but it was hard for me to read the source and understand what was
2012 Oct 24
0
[LLVMdev] Fwd: Debugging/Fixing 'Interval not live at use' errors
Hi Stephen, > I'm not entirely sure what is wrong here - I assume it has something to do > with my 'special' instruction LDri_ab. This instruction is a load with an > 'address writeback' - ld.ab r0, [r1, 5] is equivalent to ld r0, [r1]; add > r1, r1, 5. As it was very difficult to match such behaviour automatically, I > actually only generate them manually for
2008 Jul 10
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Cool, that worked. New patch attached... Cheers, Gary Evan Cheng wrote: > Just cast both values to const TargetRegisterClass*. > > Evan > > On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: > > Evan Cheng wrote: > > > How about? > > > > > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : > > > &PPC:G8RCRegClass; >