similar to: Bridging Issues with Xen

Displaying 20 results from an estimated 400 matches similar to: "Bridging Issues with Xen"

2010 Nov 11
2
[LLVMdev] defining types structurally equivalent to a recursive type
Hi all, http://www.llvm.org/docs/ProgrammersManual.html#BuildRecType suggests us to define recursive types via opaque and refine. Since LLVM has structural types, %rt = type { %rt* } and %rt1 = type { %rt* } should be same structurally. I tested the following code, %rt = type { %rt* } %rt1 = type { %rt* } define i32 @main() nounwind { entry: %0 = alloca %rt ;
2010 Nov 11
0
[LLVMdev] defining types structurally equivalent to a recursive type
On Thu, Nov 11, 2010 at 8:28 AM, Jianzhou Zhao <jianzhou at seas.upenn.edu> wrote: > Hi all, > > http://www.llvm.org/docs/ProgrammersManual.html#BuildRecType suggests > us to define recursive types via opaque and refine. Since LLVM has > structural types, %rt = type { %rt* } and %rt1 = type { %rt* } should > be same structurally. I tested the following code, > > %rt =
2008 Nov 17
2
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
I have a very strange and complicate H/W platform. It has many registers in one format. The register format is: ------------------------------ ---------------------------------------------------------------------------------------- | 24-bit | 24-bit | 24-bit | 24-bit |
2008 Nov 18
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
Why not model each channel as a separate physical register? Evan On Nov 17, 2008, at 6:36 AM, Wei wrote: > I have a very strange and complicate H/W platform. > It has many registers in one format. > The register format is: > > ------------------------------ > ---------------------------------------------------------------------------------------- > | 24-bit
2008 Nov 21
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
24 bit is not unusual in the DSP world. I suppose int == 24 bit integer for some of these chips? There isn't a i24 simple type. However, you can create an extended integer type. See getExtendedIntegerVT. It's almost guaranteed you will have to change a chunk of target independent codegen to support the use of an extended type though. Evan On Nov 20, 2008, at 4:46 AM, Wei wrote:
2008 Nov 20
4
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
Because each channel contains 24-bit, so.. what is the llvm::SimpleValueType I should use for each channel? the current llvm::SimpleValueType contains i1, i8, i16, i32, i64, f32, f64, f80, none of them are fit one channel (24-bit). I think I can use i32 or f32 to represent each 24-bit channel, if the runtime result of some machine instructions exceeds 23-bit (1 bit is for sign), then it is an
2008 Nov 20
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
This is similar to ATI's R300/R420 pixel shaders. I'm familiar with this hardware, but not really an LLVM expert (working on a code generator myself, but learning as I go). Do you have 24-bit integer operations, or just floating point? What about load/store? Are you looking to run large C programs with complex data structures, or just comparatively simple math functions (i.e. a
2008 Nov 22
2
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
Do you mean MVT::getIntegerVT? Because I can not find getExtendedIntegerVT in the llvm source codes. I am excited seeing this function, however I have the following more questions. 1) You mention I will have to change not small amount of target indenpendent codegen codes to support this extended type. Are there any document to describe how to do such kind modification? I see there is a
2008 Nov 22
2
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
I have 24-bit integer operations as well as 24-bit floating point (s7.16) operations. The H/W supports load/store instructions, however, they does suggest us not to use these load/store instructions besides debugging purpose. That is to say, you can imagine we don't have load/store instructions, we don't have memory, we just have registers. I will run OpenGL shading laugnage programs on
2005 Nov 25
7
tcpdump not working with imq0 devices
On my debian woody (kernel 2.4.31) the tcpdump doesn''t work with imq0 devices. If I try to tcpdump imq devices there is no packet seen: [...] rt1:~# tcpdump -n -i imq0 Warning: arptype 65535 not supported by libpcap - falling back to cooked socket tcpdump: WARNING: imq0: no IPv4 address assigned tcpdump: verbose output suppressed, use -v or -vv for full protocol decode listening on
2008 Nov 22
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
On Nov 22, 2008, at 11:03 AM, Wei wrote: > I have 24-bit integer operations as well as 24-bit floating point > (s7.16) operations. > > The H/W supports load/store instructions, however, they does suggest > us not to use these load/store instructions besides debugging purpose. > That is to say, you can imagine we don't have load/store instructions, > we don't have
2008 Nov 24
2
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
> The machines I worked with didn't support any integer ops, but GLSL > let us get by with "emulated" 16 bit integers (storing and operating > on them as floating point; divides required truncation after the op - > that sort of thing). Although my platform indeed supports integer operations, however, it only supports integer +,-,*, not /. The document says if I need to
2013 Feb 20
1
Access puppet hash name in templates
Hi, I''ve defined a hash like so in my nodes.pp: net::addr { "eth5": rt => { rt1 => { address => ''192.168.10.0'', netmask => ''255.255.255.0'', gateway => ''192.5.28.19'', src =>
2010 Feb 08
2
Proposals for making configure_from_network function works in f13
Hi I am running a pxe diskless node in f13 and I have some proposals to make ovirt-early working in this version. nash is no more available (nash/mkinitrd is replaced by dracut), so this following command fails : "echo "network --device $DEVICE --bootproto dhcp" | nash" it makes the network configuration incomplete. I replace the linuxrc command by dhclient and it's
2017 Oct 11
1
[PATCH v1 01/27] x86/crypto: Adapt assembly for PIE support
Change the assembly code to use only relative references of symbols for the kernel to be PIE compatible. Position Independent Executable (PIE) support will allow to extended the KASLR randomization range below the -2G memory limit. Signed-off-by: Thomas Garnier <thgarnie at google.com> --- arch/x86/crypto/aes-x86_64-asm_64.S | 45 ++++++++----- arch/x86/crypto/aesni-intel_asm.S
2017 Dec 15
2
EFI PXE Server - pxelinux.0 equivalent?
Hi all - I'm not sure if it's appropriate to ask this here, but I don't see this question explicitly answered anywhere. Is there an EFI version of "pxelinux.0" that will function basically the same way and read the same pxelinux.cfg/default menu files? I've got a really dodgy grubx64.efi EFI PXE menu up at work, but it can't load the 1.2 gigabyte LiveCD that we use
2005 Jun 29
0
Upload shaper problem
Hello guys, I am experiencing a strange behaviour with HTB. Here is my situation: Test PC -------- internet ------------- ISP ----- fiber connection --------- (eht2) RT1 (eth1) --------- wireless connection ------------ (eth4) RT2 (eth0) -------- users RT1 - Slackware router RT2 - Slackware router Delay between Test PC and ISP is approx 450 ms. I have the following shapers
2003 Dec 29
1
Agent setup
Dear Group, I have been successful in setting up the Agents, queues and getting agents to log in. Is there a way that I could configure the system so that the agent is called back. i.e. the agent logs into the system, a call is destined for them and their phone rings. If some one has this setup I would be very interested in hearing from them. Warm Regards and Thanks --------------- Shad
2004 Jun 02
0
how to route based on link load?
hello, i want to know if there is any method to route traffic based on the load of a link. imagine the following scenario: +----------+ +------+ +------+ +----------+ | subnet 1 |#####| rt 1 |--------| rt 2 |#####| subnet 2 | +----------+ +------+ +------+ +----------+ \ / \ +------+ /
2006 Dec 17
2
Collapsing across trials
Hello, My ultimate goal is a repeated measures (mixed model) ANOVA, however, my present question is about how to reorganize my data into the format that the ANOVA commands expect. In particular, how to collapse across trials. (I am using the tutorial at [http://personality-project.org/r/r.anova.html] for the mixed model ANOVA) The data I am using looks like this. A subject sees 10 trials per