similar to: [PATCH] fixup 3dnow! support

(Applies cleanly only on top of the previously sent SVM/LBR patch.) Signed-off-by: Jan Beulich <jbeulich@novell.com> Index: 2007-08-08/xen/arch/x86/hvm/svm/svm.c =================================================================== --- 2007-08-08.orig/xen/arch/x86/hvm/svm/svm.c 2007-08-08 11:40:11.000000000 +0200 +++ 2007-08-08/xen/arch/x86/hvm/svm/svm.c 2007-08-08 11:43:53.000000000 +0200

- use __clear_bit() rather than clear_bit() - use switch statements instead of long series of if-s - eliminate pointless casts (Applies cleanly only on top of the previously sent SVM/EFER patch.) Signed-off-by: Jan Beulich <jbeulich@novell.com> Index: 2007-08-08/xen/arch/x86/hvm/hvm.c =================================================================== ---

Linux 2.6.19 (x86-64) makes use of this feature if available, but Xen (validly) fails the attempt to write the respective MSR. Hence the feature must be hidden from PV guests. Signed-off-by: Jan Beulich <jbeulich@novell.com> Index: 2007-01-16/xen/arch/x86/traps.c =================================================================== --- 2007-01-16.orig/xen/arch/x86/traps.c 2007-01-15

From: Borislav Petkov <bp at suse.de> Use boot_cpu_has() instead. Signed-off-by: Borislav Petkov <bp at suse.de> Cc: virtualization at lists.linux-foundation.org Cc: sparmaintainer at unisys.com --- arch/x86/events/intel/cstate.c | 2 +- arch/x86/events/intel/uncore.c | 2 +- arch/x86/include/asm/cpufeature.h | 1 -

From: Borislav Petkov <bp at suse.de> Use boot_cpu_has() instead. Signed-off-by: Borislav Petkov <bp at suse.de> Cc: virtualization at lists.linux-foundation.org Cc: sparmaintainer at unisys.com --- arch/x86/events/intel/cstate.c | 2 +- arch/x86/events/intel/uncore.c | 2 +- arch/x86/include/asm/cpufeature.h | 1 -

From 291adaf4ad6174c5641a7239c1801373e92e9975 Mon Sep 17 00:00:00 2001 From: Liu Jinsong <jinsong.liu@intel.com> Date: Thu, 28 Nov 2013 05:26:06 +0800 Subject: [PATCH v4 3/7] X86: MPX IA32_BNDCFGS msr handle When MPX supported, a new guest-state field for IA32_BNDCFGS is added to the VMCS. In addition, two new controls are added: - a VM-exit control called "clear BNDCFGS" - a

X86: implement PCID/INVPCID for hvm This patch handle PCID/INVPCID for hvm: For hap hvm, we enable PCID/INVPCID, since no need to intercept INVPCID, and we just set INVPCID non-root behavior as running natively; For shadow hvm, we disable PCID/INVPCID, otherwise we need to emulate INVPCID at vmm by setting INVPCID non-root behavior as vmexit. Signed-off-by: Liu, Jinsong

With the x86 instruction emulator no pretty complete, I''d like to re-submit this patch to support cmpxchg16b on x86-64 and at once rename the underlying emulator callback function pointer (making clear that if implemented, it is to operate on two longs rather than two 32-bit values). At the same time it fixes an apparently wrong emulator context initialization in the shadow code.

From: Borislav Petkov <bp at suse.de> Using static_cpu_has() is pointless on those paths, convert them to the boot_cpu_has() variant. No functional changes. Reported-by: Nadav Amit <nadav.amit at gmail.com> Signed-off-by: Borislav Petkov <bp at suse.de> Cc: Aubrey Li <aubrey.li at intel.com> Cc: Dave Hansen <dave.hansen at intel.com> Cc: Dominik Brodowski <linux

CPUID level 0x00000007:0 (ebx) is word 9, instead of word 7. ... make it consistent with native Linux. Signed-off-by: Li Xin <xin.li@intel.com> diff -r d7c755c25bb9 xen/include/asm-x86/cpufeature.h --- a/xen/include/asm-x86/cpufeature.h Sat May 28 08:58:08 2011 +0100 +++ b/xen/include/asm-x86/cpufeature.h Tue May 31 07:34:34 2011 +0800 @@ -142,7 +142,7 @@ #define X86_FEATURE_TOPOEXT

X86: expose HLE/RTM features to dom0 Intel recently release 2 new features, HLE and TRM. Refer to http://software.intel.com/file/41417. This patch expose them to dom0. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> diff -r 92e03310878f xen/arch/x86/traps.c --- a/xen/arch/x86/traps.c Wed Feb 08 21:05:52 2012 +0800 +++ b/xen/arch/x86/traps.c Mon Feb 27 02:23:42 2012 +0800 @@ -857,9

.. for both 32-bit apps in 64-bit pv guests and 32on64. This patch depends on more than just guest_context saved/restored as guest state during save/restore/migrate (namely the new fields holding callback addresses). Since the 32-bit kernel doesn''t make use of syscall (it would be possible to do so now, when running on a 64-bit hv), the compat mode guest code path for syscall

The SYSENTER instruction jumps to a pre-programmed address at privilege level 0. We must not allow execution of guest code at that privilege level, so disable sysenter when we enter the guest (and re-enable it on return). This fixes current case where guest userspace can crash host. This save/restore adds 3% to guest context switch times. (If only there were some kind of scheduler hook or

The SYSENTER instruction jumps to a pre-programmed address at privilege level 0. We must not allow execution of guest code at that privilege level, so disable sysenter when we enter the guest (and re-enable it on return). This fixes current case where guest userspace can crash host. This save/restore adds 3% to guest context switch times. (If only there were some kind of scheduler hook or

These are known to not support the feature, so we can save ourselves from emitting the resulting #GP fault recovery related message (which might worry people looking at the logs). Signed-off-by: Jan Beulich <jbeulich@suse.com> --- a/xen/arch/x86/cpu/intel.c +++ b/xen/arch/x86/cpu/intel.c @@ -204,7 +204,7 @@ static void __devinit init_intel(struct detect_ht(c); } - if

On 03/19/2014 06:07 AM, Paolo Bonzini wrote: > Il 19/03/2014 04:15, Waiman Long ha scritto: >>>> You should see the same values with the PV ticketlock. It is not clear >>>> to me if this testing did include that variant of locks? >>> >>> Yes, PV is fine. But up to this point of the series, we are concerned >>> about spinlock performance when

On 03/19/2014 06:07 AM, Paolo Bonzini wrote: > Il 19/03/2014 04:15, Waiman Long ha scritto: >>>> You should see the same values with the PV ticketlock. It is not clear >>>> to me if this testing did include that variant of locks? >>> >>> Yes, PV is fine. But up to this point of the series, we are concerned >>> about spinlock performance when

Locking is always an issue in a virtualized environment because of 2 different types of problems: 1) Lock holder preemption 2) Lock waiter preemption One solution to the lock waiter preemption problem is to allow unfair lock in a virtualized environment. In this case, a new lock acquirer can come and steal the lock if the next-in-line CPU to get the lock is scheduled out. A simple unfair queue

This follows Linux commit 39fe05e58c5e448601ce46e6b03900d5bf31c4b0, noticing that all this setup is pointless when ARAT support is there, and knowing that on SLED11''s native kernel it has actually caused S3 resume issues. A question would be whether HPET legacy interrupts should be forced off in this case (rather than leaving whatever came from firmware). Signed-off-by: Jan Beulich

Hey guys, I just released my new MacOSX-based OpenAL implementation...part of it is a Ogg Vorbis decoder based on the 1.0 reference libraries. I spent some time optimizing them and found that many of the hotspots in libvorbis are perfect candidates for vectorization, so I wrote Altivec versions of them. The end result? Decoding of a .ogg file is between 30 and 50% faster on a Mac with an