similar to: C API - no NULL pointer guarantee?

? Sat, 27 Jul 2024 14:36:20 +0300 "Erez Shomron" <r-mails at erezsh.org> ?????: > I'm working on bindings for the API (for zig), and was wondering if > the R's C API guarantees it won't return null pointers? The only > reference I found in the "Writing R Extensions" manual where this not > the case is `R_tryEval` and `R_tryEvalSilent`. Based on

Thank you Ivan, At this point, without it being documented explicitly, I tend to lean on the safe side. If the non-null assumption is ever incorrect, on debug and safe builds unwrapping is an assert that will guarantee to crash R. While the source code has plenty of NULL checks, also for some SEXP, it's hard to tell just from grepping if any are related to the public API or not. Secondly

Erez, I think the API is very explicit about this, NULL is not an accepted input for any function taking SEXP by design. The special case of try*Eval() return values can be taken as a case where the resulting object is not actually SEXP but rather a special type which can be NULL (=failure) or SEXP. It may be even perhaps useful to declare it as a separate type to make this clearer, but I

On Apr 15, 2013, at 2:02 PM, Francois Pichet <pichet2000 at gmail.com> wrote: > Hi, > > Let's say we have a 32-bit architecture where 64-bit additions are done using 2 operations. > > Instructions are defined as follow in TableGen: > defm ADD64 : ALU32<"add", 1, 1, addc>; > defm ADD64C : ALU32<"addrc", 1, 2, adde>; > >

Hi to all! Sorry for my English :) The problem: We have a shaper software based on tc linux shaper/filter. This software (''shaper'') work with one interface (''eth0'') with fixed bandwidth and limit user (above 100 user each time) bandwidth accordingly user''s tariff plan. User traffic filter based on destination (user) ip. There a lot of connection

Hi Francois, If you model the effect of your carry on the instructions, the scheduler (and the other backend passes) should ensure that nothing that affects the carry will be inserted between your two instructions (assuming they are issued with nothing affecting the carry in between in the first place). Therefore, you shouldn’t have to force them to be stuck together. If you still do, what Jakob

Hi Jakob, If glue operands are used by the scheduler to keep instructions together, why can't the register allocator also do this? Regards, Sam On 15/04/2013 23:12, Jakob Stoklund Olesen wrote: > On Apr 15, 2013, at 2:02 PM, Francois Pichet <pichet2000 at gmail.com> wrote: > >> Hi, >> >> Let's say we have a 32-bit architecture where 64-bit additions are

I am looking for a simple way to guarantee to each flow going through my traffic control point 1/numflows of bandwidth. I thought using SFQ would do this effectively but it appears to be quite unfair: a very high speed download that fills the pipe easily starves smaller flows to the point where it becomes unusable (especially if they are at all interactive) Because numflows is dynamic,

Using bundles here looks like a fragile way to handle that, IMHO. Really, using a pseudo instruction seems the best approach for you. For instance, you can match your add64 during isel with your pseudo instruction and expand it just before emitting the assembly file (add a pass using the hook: addPreEmitPass on your target). -Quentin On Apr 15, 2013, at 2:37 PM, Francois Pichet <pichet2000

I'd like to generate an indirect call instruction that will end up as a call via memory and not register. The address of the target is a constant. For example, something like %25 = load i64, i64* @get_Now %26 = inttoptr i64 %25 to i64 ()* %27 = call i64 %26() may end up as mov rsi,qword ptr [00007FF658381070] call rsi or as call qword ptr [00007FF658381070] If I want to

Hi, Let's say we have a 32-bit architecture where 64-bit additions are done using 2 operations. Instructions are defined as follow in TableGen: defm ADD64 : ALU32<"add", 1, 1, addc>; defm ADD64C : ALU32<"addrc", 1, 2, adde>; Let's assume that the carry bit is implicit and that the 2 operations must *always* be stuck together for the 64-bit add to

I really have to force them to stuck together otherwise the carry will just not work. How about wrapping the 2 instructions in a bundle? Would that be a way? http://llvm.org/docs/CodeGenerator.html#machineinstr-bundles On Mon, Apr 15, 2013 at 5:24 PM, Quentin Colombet <qcolombet at apple.com>wrote: > Hi Francois, > > If you model the effect of your carry on the instructions, the

> > > The GCC test-suite, AFAIK, has very poor quality on what's considered > a pass or a failure, ????? What makes you say this > and it's common to release GCC with thousands of > failures on those tests. Also not correct. https://gcc.gnu.org/gcc-4.4/criteria.html It is a zero regression policy for primary platforms. Look, I love LLVM as much as the next

I've been playing with OrcJIT a bit, and from the looks of it I can (like in the previous JIT I suppose?) ask for a function to be re generated. If I've given the address of the function that LLVM gave me to an external party, do "I" need to ensure thread-safety? Or is it safe to ask OrcJIT to re generate code at that address and everything will work magically? I'm

Hi, All, After searching the whole project, I only find about ~10000 cases from "llvm/test" for each commit, and a separate testsuit wrote with high level language(i.e. C/C++) to verify the quality and performance. As a general Backend, you know, it must be strong enough to cope with all the IR generated by Frontend. I cannot believe what I see. Did I miss something ? As far as I know,

Hi Sanjoy, > You need the hijack-return-pc approach *in addition* to a call-site > patching approach. Modifying the return PC lets you guarantee that > nothing will *return* into the old generated code. To guarantee that > nothing will *call* into it either you could use a double indirection > (all calls go through a trampoline) or patchpoints. You need to hijack the return

Hello to all people there . Can i guarantee ICMP respond time no metter how loaded is internet line . i have typical NATed enviroiment like External IP |linux router| LAN - 192.168.0.0/24 i have example setup with IMQ but is it possible to be done also if i attache htb to eth0 and eth1 for example . if i start shaper ping i better that without shaper but it''s not guarantted i mean

Hi Sanjoy, >> (1) Replacing function bodies at the same address is impossible if the >> function is already on the stack: You'd be replacing a definition that >> you're later going to return through. > > If the function you wish to replace is active on the stack, you can > replace the return PC that was going to return into that active frame > with a PC

Hello, I have problems setting up HTB. This is my setup : NET 1024/256 ADSL || eth1 Linux Firewall eth0 || LAN 10.a.a.a I want to GUARANTEE for an IP (10.x.y.z) a 800kbit bandwidth for HTTP download. But When 10.x.y.z does no HTTP download, other trafic must get the whole bandwidth, of course. The script I use (see below) is quite the same as presented at (the greeeeat page) :

Hi, I'm trying to using pspline in bic.surv{BMA}. ############################# library(BMA) library(survival) data(veteran) test.bic.surv<- bic.surv(Surv(time,status) ~ karno+pspline(age,df=3)+diagtime+prior, data = veteran, factor.type = TRUE) summary(test.bic.surv, conditional=FALSE, digits=2) ############################# The results are: