similar to: [PATCH][next] drm/nouveau/fifo/gk104: remove redundant variable ret

On Tue, Jan 16, 2024 at 11:16:09AM +0000, Colin Ian King wrote: > The variable ret is being assigned a value but it isn't being > read afterwards. The assignment is redundant and so ret can be > removed. > > Cleans up clang scan build warning: > warning: Although the value stored to 'ret' is used in the enclosing > expression, the value is never actually read from

On 1/16/24 13:31, Dan Carpenter wrote: > On Tue, Jan 16, 2024 at 11:16:09AM +0000, Colin Ian King wrote: >> The variable ret is being assigned a value but it isn't being >> read afterwards. The assignment is redundant and so ret can be >> removed. >> >> Cleans up clang scan build warning: >> warning: Although the value stored to 'ret' is used in

On Tue, Jan 23, 2024 at 12:04:23AM +0100, Danilo Krummrich wrote: > On 1/16/24 13:31, Dan Carpenter wrote: > > On Tue, Jan 16, 2024 at 11:16:09AM +0000, Colin Ian King wrote: > > > The variable ret is being assigned a value but it isn't being > > > read afterwards. The assignment is redundant and so ret can be > > > removed. > > > > > >

When `nouveau_dmem_copy_one` is called, the following error occurs: [272146.675156] nouveau 0000:06:00.0: fifo: PBDMA9: 00000004 [HCE_PRIV] ch 1 00000300 00003386 This indicates that a copy push command triggered a Host Copy Engine Privileged error on channel 1 (Copy Engine channel). To address this issue, modify the Copy Engine channel to allow privileged push commands Fixes: 6de125383a5cc

From: Yonatan Maman <Ymaman at Nvidia.com> When `nouveau_dmem_copy_one` is called, the following error occurs: [272146.675156] nouveau 0000:06:00.0: fifo: PBDMA9: 00000004 [HCE_PRIV] ch 1 00000300 00003386 This indicates that a copy push command triggered a Host Copy Engine Privileged error on channel 1 (Copy Engine channel). To address this issue, modify the Copy Engine channel to allow

This is an initial series of patches to improve channel recovery on Turing GPUs with the goal of improving reliability enough to eventually enable SVM for Turing. It's likely follow up patches will be required to fully address problems with less trivial workloads than what I have been able to test thus far. This series primarily addresses a number of hardware changes to interrupt layout and

+Aaron because i think he uses scan-build on Windows more or less successfully. I won't have time for setting up a Windows machine for myself in the nearest future. Could you tell us exactly what you're doing and what exactly does it print to console, more in the spirit of http://www.catb.org/~esr/faqs/smart-questions.html ? > scan-build: Not supported for windows. Exiting...

The offset should be 8 on Kepler and later. Signed-off-by: Vince Hsu <vinceh at nvidia.com> --- drm/nouveau/nvkm/engine/fifo/gk104.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Hi, According to the header[1] the offset for engine status register is 8. [1] https://github.com/kfractal/nouveau/blob/hwref/drm/nouveau/include/nvkm/hwref/gk104/fifo.h Thanks, Vince diff --git

From: Xia Yang <xiay at nvidia.com> Fix the channel id bit mask in FIFO schedule timeout error handling. FIFO_ENGINE_STATUS_NEXT_ID is bit 27:16 thus 0x0fff0000. FIFO_ENGINE_STATUS_ID is bit 11:0 thus 0x00000fff. Signed-off-by: Xia Yang <xiay at nvidia.com> Reviewed-by: Alexandre Courbot <acourbot at nvidia.com> --- drm/nouveau/nvkm/engine/fifo/gk104.c | 4 ++-- 1 file

On Tue, Mar 01, 2016 at 04:59:05PM +0900, Alexandre Courbot wrote: > > Eric, since you reported the regression on the first version, would you mind trying > this one and giving us your Tested-by? I have tested it on dGPU but unfortunately > could not set it up in an optimus-like manner, with power management kicking in. > Thanks. I've tested Linux 4.5-rc6 with your patch

On Wed, Mar 2, 2016 at 12:53 PM, Eric Biggers <ebiggers3 at gmail.com> wrote: > On Tue, Mar 01, 2016 at 04:59:05PM +0900, Alexandre Courbot wrote: >> >> Eric, since you reported the regression on the first version, would you mind trying >> this one and giving us your Tested-by? I have tested it on dGPU but unfortunately >> could not set it up in an optimus-like

On Wed, Mar 2, 2016 at 6:07 PM, Alexandre Courbot <gnurou at gmail.com> wrote: > On Wed, Mar 2, 2016 at 12:53 PM, Eric Biggers <ebiggers3 at gmail.com> wrote: >> On Tue, Mar 01, 2016 at 04:59:05PM +0900, Alexandre Courbot wrote: >>> >>> Eric, since you reported the regression on the first version, would you mind trying >>> this one and giving us your

On Mon, Mar 07, 2016 at 11:10:16AM +0900, Alexandre Courbot wrote: > > Hi Eric, just to follow up - are you still happy with this patch? Yes, I still haven't had any problems with it.

On Mon, Mar 7, 2016 at 11:32 AM, Eric Biggers <ebiggers3 at gmail.com> wrote: > On Mon, Mar 07, 2016 at 11:10:16AM +0900, Alexandre Courbot wrote: >> >> Hi Eric, just to follow up - are you still happy with this patch? > > Yes, I still haven't had any problems with it. Awesome. Clear to add your Tested-by?

Presumably we can never actually hit this return, but static checkers complain that we should unlock before we return. Signed-off-by: Dan Carpenter <dan.carpenter at oracle.com> diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c index 3a24788c3185..a7e55c422501 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c +++

2015-08-12 16:37 GMT+09:00 Afzal Mohammed <afzal.mohd.ma at gmail.com>: > Hi, > > On Wed, Aug 12, 2015 at 04:12:15PM +0900, Alexandre Courbot wrote: > >> Could you let me know what your card is? It may be useful to know the >> range of affected cards when trying to fix this. > > grep of nouveau on dmesg as follows, if the following information is > not

A channel may still be processed by the PBDMA even after removal, unless it is properly kicked. Some chips are more sensible to this than others, with GM20B triggering the issue very easily (the PBDMA will try to fetch methods from the previously-removed channel after a new one is added). Make sure this cannot happen by kicking the channel right after it is disabled, and before the new runlist is

On Wed, Aug 12, 2015 at 3:00 PM, Afzal Mohammed <afzal.mohd.ma at gmail.com> wrote: > Hi, > > On Wed, Aug 12, 2015 at 01:17:38PM +0900, Alexandre Courbot wrote: >> This reverts commit 1addc1264852 >> >> This commit seems to cause crashes in gk104_fifo_intr_runlist() by >> returning 0xbad0da00 when register 0x2a00 is read. Since this commit was >>

Signed-off-by: ZhiHu <huzhi001 at 208suo.com> --- .../gpu/drm/nouveau/nvkm/engine/fifo/gk104.c | 40 ++++++++++++++----- 1 file changed, 29 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c index d8a4d773a58c..b99e0a7c96bb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c +++

not sure how i got signed up for this and i don?t see a way to unsubscribe. this is flooding my email with things i don?t care about. On Fri, Jul 14, 2023, at 1:14 AM, huzhi001 at 208suo.com wrote: > Signed-off-by: ZhiHu <huzhi001 at 208suo.com> > --- > .../gpu/drm/nouveau/nvkm/engine/fifo/gk104.c | 40 ++++++++++++++----- > 1 file changed, 29 insertions(+), 11 deletions(-)