similar to: ZFS raidz1 replacing failing disk

I recently had an X86 system (running Nexenta Elatte, if that matters -- b101 kernel, I think) suffer hardware failure and refuse to boot. I''ve migrated the disks into a SPARC system (b115) in an attempt to bring the data back online while I see about repairing the former system. However, I''m having some trouble with the import process: hydra# zpool import pool: tank id:

hello: I have 3 data.frame objects. First df object: Of dim (149,31). Columns 2:31 are marked as T1..T14 and N1..N16. Name T1 T2 N1 T3 N2 N3 N4 T4 mu1 10 10 9 10 9 9 8 10 mu2 11 11 9 11 9 9 9 11 ... muN 12 12 9 11 9 9 8 12 Second df object: of Dim (50000,31). Columns 2:31 are maked as T1...T14 and N1..N16.

Question for 'experts' in LP using R (using the lpSolve package, say) -- which does not apply to me for the sort of problem I describe below. I've run any number of LP's using lpSolve in R, but all of them to date have objective and constraint functions that both contain the same variables. This lets you set up a LHS and RHS matrix/vector that are symmetrical. But, for a

also i further run the following command; llc -debug filer-knl_o3.ll and its output is attached here. by looking at the output can we say that legalization runs fine and the error is due to instruction selection/ pattern matching which is not yet implemented? so do i need to worry and try to correct it at this stage or should i move forward to implement instruction selection/ pattern matching?

Apart from the fact that the statement "such that t1+t2+t3+t4=2970 (as it must)" is not correct, the LP can be implemented as follows: library(lpSolve) LHS <- rbind( c(0,0,0,0, 1, 0, 0,0), c(1,0,0,0,-1, 1, 0,0), c(0,1,0,0, 0,-1, 1,0), c(0,0,1,0, 0, 0,-1,1), cbind(-diag(4),diag(4)), c(0,0,0,0,0,1,0,0), c(0,0,0,0,0,0,1,0), c(0,0,0,0,0,0,0,1) ) RHS <-

Hello, i am experimenting with the increase in register/ vector width to 64 elements of 32 bits instead of 16 in x86 backend. for eg. i have a loop with 65 iterations; if my IR generates v64i32 and 1 scalar, still the backend breaks the v64i32 into 4 v16i32. i want it to retain v64i32. like if there are 128 elements in loop then it should break it into 2 v64i32 instructions. in order to do this i

Is there an established way of disabling a DAG combine on a per target basis, where it appears to be detrimental to the generated code? Writing if (!mytarget) in DAGCombiner.cpp works but tends to be erased by git merge and generally doesn't look ideal. Writing the inverse transform in target specific code doesn't work in this instance and in general creates an infinite loop. Guidance

I come across a situation that I am having a hard time to understand. When I compile the following code : char *tst( char *dest, const char *src, unsigned int len ) { for (int i=0 ; i<len ; i++) { dest[i] = src[i]; } return dest; } Clang generates this for the ‘for’ body: for.body: ; preds = %for.cond %arrayidx = getelementptr inbounds i8,

Hi All, I want to be able to change the labe size on a tree when using ape package so that the graph can look nicer, but don't know how. Playing with the "font" doesn't seem to help. (Right now the labels barely show.) Thanks for your help! Code I'm using now #------------------------- t1 = "(((1:77.37,2:77.37):9.4,4:86.77):7.56,3:94.33);" t2 =

On 10/20/2016 9:28 AM, Cameron McInally via llvm-dev wrote: > I should have attached the generated asm to save some trouble. > Apologies for that and attaching now... > > > > On Thu, Oct 20, 2016 at 12:26 PM, Cameron McInally > <cameron.mcinally at nyu.edu> wrote: >> On Thu, Oct 20, 2016 at 12:05 PM, Mehdi Amini <mehdi.amini at apple.com> wrote:

Hi, I am receiving an LLVM Error from a custom 16-bit backend I am creating. I am having trouble understanding the error/problem and how to go about solving it. The error is: LLVM ERROR: Cannot select: t29: i32,ch = load<LD2[%x.addr], anyext from i16> t14, FrameIndex:i16<0>, undef:i16 t7: i16 = FrameIndex<0> t9: i16 = undef In function: mul_add Can anyone provide any

Hi everyone, I am trying to accomplish a small task that is giving me quite a headache. I would like to automatically generate a series of matrices and give them successive names. Here is what I thought at first: t1<-matrix(0, nrow=250, ncol=1) for(i in 1:10){ t1[i]<-rnorm(250) } What I intended was that the loop would create 10 different matrices with a single column of 250

Thank You. On Fri, Jul 7, 2017 at 10:03 AM, Craig Topper <craig.topper at gmail.com> wrote: > Yes, that error is from instruction selection. I think your legalization > changes worked fine. > > ~Craig > > On Thu, Jul 6, 2017 at 8:21 PM, hameeza ahmed via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> also i further run the following command;

On Tue, Jun 25, 2019 at 9:59 AM Tim Northover <t.p.northover at gmail.com> wrote: > On Tue, 25 Jun 2019 at 06:26, Gleb Popov via llvm-dev > <llvm-dev at lists.llvm.org> wrote: > >> While the store is being selected LLVM will just treat the value being > >> stored as a generic pointer-width integer unless you have written a > >> specific pattern for

Hi, I'm implementing the built_vector as an IMPLICIT_DEF followed by INSERT_SUBREGs. This approach is the one of the SPARC architecture. def : Pat<(build_vector (f32 fpimm:$a1), (f32 fpimm:$a2)), (INSERT_SUBREG(INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), (i32 (COPY_TO_REGCLASS (MOVSUTO_A_iSLo (bitcast_fpimm_to_i32 f32:$a1)), FPUaOffsetClass)), A_UNIT_PART),

Have you read http://llvm.org/docs/WritingAnLLVMBackend.html and http://llvm.org/docs/CodeGenerator.html ? http://llvm.org/docs/WritingAnLLVMBackend.html#instruction-selector describes how to define a store instruction. -Eli On 7/6/2017 6:51 PM, hameeza ahmed via llvm-dev wrote: > Please correct me i m stuck at this point. > > On Jul 6, 2017 5:18 PM, "hameeza ahmed"

So I installed CentOS Stream 9 on a new Lenovo T14 Gen 4 Intel. I have a 4x1 HDMI KVM with external monitor. When switching the KVM, apps move between displays / workspaces in erratic ways. More specifically, when switching out, apps on the external display usually move to the laptop display. This sorta makes sense for a laptop with an external display. When the external display is

Hey all, I'm pretty new to Asterisk and VoIP in general, so I'm hoping I can get a bit of help here. First I'll explain my setup, and then my problem. Right now I have a Cisco 3640 with a VIC2FXO card in it which has 2 FXO ports. I have an analog phone line plugged into the first port (voice-port 1/0/0). I've got it setup so that calls coming into that analog line are

Hi, I’ve been thinking about what the strategy to use for boolean values in GlobalISel. There are a few semantic and mechanical issues I’ve encountered. For background, on AMDGPU, there are two kinds of bool/s1 values. Contextually, a real boolean value will either be a 1-bit scalar condition (in a non-allocatable physical condition register, which will need to be copied to an allocatable class

Hi List, I have start and end times of events structure(list(start = c("15:00", "15:00", "15:00", "11:00", "14:00", "14:00", "15:00", "12:00", "12:00", "12:00", "12:00", "12:00", "12:00", "12:00", "12:00", "12:00", "12:00",