similar to: extracting pdf tables...

Clearly the column names are different. You need to decide what to do about that. Choose the subset of dataframes where the column names are the same? Rename columns? Omit some columns? Add missing columns filled with NA? On April 9, 2023 10:22:32 AM PDT, akshay kulkarni <akshay_e4 at hotmail.com> wrote: >Dear members, > I am extracting a pdf table by the

Dear Jeff, I want to rbind. Thanking you, Yours sincerely, AKSHAY M KULKARNI ________________________________ From: R-help <r-help-bounces at r-project.org> on behalf of Jeff Newmiller <jdnewmil at dcn.davis.ca.us> Sent: Sunday, April 9, 2023 11:57 PM To: r-help at r-project.org <r-help at r-project.org> Subject: Re: [R] extracting pdf tables... Sorry, did not

Dear Jeff, Thanks for your reply. I have the following: > colnames(IDT[[4]]) [1] "X168" "TATA.MOTORS.LIMITED" "TATAMOTORS" "X4" THe above has to be the first row of IDT[[4]]. The first row is getting parsed as the column name. How do you make that the first row of IDT[[4]]? Thanking you, Yours sincerely,

Dear all, I am quite new to R; facing certain problems: Say, I have a text file( named as "try"): Year C1 C2 C3 C4 C5 C6 Y1 3.5 13.8 9.5 6.8 0.4 24.2 Y2 3.8 13.9 9.9 7.6 0.7 12.8 Y3 4.5 14.5 14.2 9.2 0.6 14.5 Y4 5.9 16.2 24.6 12.7 0.2 24.3 Y5 7.2 20.4 40.6 18.2 0.8 28.2 Y6 5.9 18.6 37.4 14.5 0.3 36.9 Y7 8.0 16.1 88.6 24.1 0.1 34.6 Y8 13.6 21.1 56.3 19.0 0.7 33.3 I wish to import the

This makes the IDT unconditionally read-only. This primarily removes the IDT from being a target for arbitrary memory write attacks. It has an added benefit of also not leaking (via the "sidt" instruction) the kernel base offset, if it has been relocated. Signed-off-by: Kees Cook <keescook at chromium.org> Cc: Eric Northup <digitaleric at google.com> ---

This makes the IDT unconditionally read-only. This primarily removes the IDT from being a target for arbitrary memory write attacks. It has an added benefit of also not leaking (via the "sidt" instruction) the kernel base offset, if it has been relocated. Signed-off-by: Kees Cook <keescook at chromium.org> Cc: Eric Northup <digitaleric at google.com> ---

Make a copy of the IDT (as seen via the "sidt" instruction) read-only. This primarily removes the IDT from being a target for arbitrary memory write attacks, and has the added benefit of also not leaking the kernel base offset, if it has been relocated. We already did this on vendor == Intel and family == 5 because of the F0 0F bug -- regardless of if a particular CPU had the F0 0F bug

Make a copy of the IDT (as seen via the "sidt" instruction) read-only. This primarily removes the IDT from being a target for arbitrary memory write attacks, and has the added benefit of also not leaking the kernel base offset, if it has been relocated. We already did this on vendor == Intel and family == 5 because of the F0 0F bug -- regardless of if a particular CPU had the F0 0F bug

On Tue, Feb 11, 2020 at 5:53 AM Joerg Roedel <joro at 8bytes.org> wrote: > > From: Joerg Roedel <jroedel at suse.de> > > With SEV-ES, exception handling is needed very early, even before the > kernel has cleared the bss segment. In order to prevent clearing the > currently used IDT, move the IDT to the data segment. Ugh. At the very least this needs a comment in the

On Tue, Feb 11, 2020 at 5:53 AM Joerg Roedel <joro at 8bytes.org> wrote: > > From: Joerg Roedel <jroedel at suse.de> > > With SEV-ES, exception handling is needed very early, even before the > kernel has cleared the bss segment. In order to prevent clearing the > currently used IDT, move the IDT to the data segment. Ugh. At the very least this needs a comment in the

Morning, I am going to treat this as a rooted box and reinstall from scratch, but any thoughts appreciated: This is a Trixbox Server based on Centos, running kernel 2.6.18-53.1.4.el5 SMP The phone system stopped working but this was traced to a configuration error with a replacement switch (it did not get added to the vlan properly), which meant that Trixbox could not see any DNS servers and

On Mon, Aug 24, 2020 at 10:54:37AM +0200, Joerg Roedel wrote: > +#ifdef CONFIG_AMD_MEM_ENCRYPT > +static void set_early_idt_handler(gate_desc *idt, int n, void *handler) > +{ > + struct idt_data data; > + gate_desc desc; > + > + init_idt_data(&data, n, handler); > + idt_init_desc(&desc, &data); > + native_write_idt_entry(idt, n, &desc); > +} >

On Mon, Aug 24, 2020 at 10:54:37AM +0200, Joerg Roedel wrote: > +#ifdef CONFIG_AMD_MEM_ENCRYPT > +static void set_early_idt_handler(gate_desc *idt, int n, void *handler) > +{ > + struct idt_data data; > + gate_desc desc; > + > + init_idt_data(&data, n, handler); > + idt_init_desc(&desc, &data); > + native_write_idt_entry(idt, n, &desc); > +} >

I am having problems installing a custom int3 handler from a com32 app. Here is what I have tried: void int3_handler() { put_str("int3!!!"); __asm__("iret"); } void init_handlers() { struct { unsigned long limit : 16; unsigned long base : 32; } __attribute__((packed)) idtr; __asm__("sidt

I was able to install Brilliant Photo, but when I try to run it I get this: dotancohen@ety:~/.wine/drive_c/Program Files/Brilliant Labs/BrilliantPhoto$ wine BrilliantPhoto.exe fixme:ntdll:TIME_GetTZAsStr Can't match system time zone name "IDT", bias=-180 and dst=1 to an entry in TZ_INFO. Please add appropriate entry to TZ_INFO and submit as patch to wine-patches

> On Feb 12, 2020, at 3:55 AM, Joerg Roedel <joro at 8bytes.org> wrote: > > ?On Tue, Feb 11, 2020 at 02:41:25PM -0800, Andy Lutomirski wrote: >>> On Tue, Feb 11, 2020 at 5:53 AM Joerg Roedel <joro at 8bytes.org> wrote: >>> >>> From: Joerg Roedel <jroedel at suse.de> >>> >>> With SEV-ES, exception handling is needed very

> On Feb 12, 2020, at 3:55 AM, Joerg Roedel <joro at 8bytes.org> wrote: > > ?On Tue, Feb 11, 2020 at 02:41:25PM -0800, Andy Lutomirski wrote: >>> On Tue, Feb 11, 2020 at 5:53 AM Joerg Roedel <joro at 8bytes.org> wrote: >>> >>> From: Joerg Roedel <jroedel at suse.de> >>> >>> With SEV-ES, exception handling is needed very

xen/arch/x86/crash.c | 116 ++++++++++++++++++++++++++++++++++----- xen/arch/x86/machine_kexec.c | 19 ++++++ xen/arch/x86/x86_64/entry.S | 34 +++++++++++ xen/include/asm-x86/desc.h | 45 +++++++++++++++ xen/include/asm-x86/processor.h | 4 + 5 files changed, 203 insertions(+), 15 deletions(-) Experimentally, certain crash kernels will triple fault very early

Are there any known or potential problems with Xen''s xmallocing the secondary cores'' IDT tables from a memory region whose physical address is higher than 4GB? Thanks Roger R. Cruz _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

In a recent conversation one of my coworkers raised a concern about memory limitations when running 32-bit guests on top of the 64-bit hypervisor. At this point the discussion is academic; I don''t know when/if we''ll ever be able to get system resources to test it, to see if the concerns that he expressed are real. So I decided to post this in hope of getting comments from the