similar to: PATCH for precompute_partition_info_sums... functions

Erik de Castro Lopo wrote: > Just like last time ( http://lists.xiph.org/pipermail/flac-dev/2015-May/005496.html ) > I'm a little nervous about this patch. > > I'll have a look at getting gcov (coverage analysis tool) working. It would be great to test it thoroughly, yes.

Erik de Castro Lopo wrote: >> 3) >> Currently there are two ia32 asm files (bitreader_asm.nasm and stream_encoder_asm.nasm) >> that are unused and not necessary to compile libFLAC: they offer no speed benefit >> and the corresponding functions were commented out (*after* the release of 1.3.0): >> >>

I've read up some more on the subject, and it seems the proper way to do this with GCC is g++ and target attributes. I've refactored the patch that way, and it indeed uses SSSE3 automatically on supporting CPUs, regardless of the build host, so this should be ideal both for home builders and distros. Getting the code to build right in c++ mode (checksum_sse2.cpp only) was a bit of an

Hi, today I tried to configure a guest using Virt-Manager and used the "copy host cpu configuration" option which resultet in a "Sandy Bridge" model. What I noticed is that for example the "aes" extension is not available in the guest even though it is available on the host cpu. This is what the host cpu looks like: model name : Intel(R) Xeon(R) CPU E5-2650 v3 @

On 06/13/2013 10:11 PM, Michael Giardino wrote: > Hi, > > I'm running libvert on a Debian 7 system. I have upgraded libvert and qemu > from source (v1.06 and 1.5.0 respectively) and the problem persists. The > guest OS is also a Debian 7 system running a non-SMP kernel. The error > message from virt-manager is > > Error starting domain: unsupported configuration:

Here I attach a preliminary version of a patch for precompute_partition_info_sums_() function that should accelerate encoding of 24-bit input data. 1) SSE2, SSSE3 and AVX2 versions of this function should be updated, too 2) the patch also changes if(FLAC__bitmath_ilog2(default_partition_samples) + bps + FLAC__MAX_EXTRA_RESIDUAL_BPS < 32) into (in effect)

Is it possible to see the source code of the open-sourced SVML? The diff file does not include the library. I searched the Internet but I could not find. Regards, Naoki Shibata On 2016/07/15 13:55, Tian, Xinmin wrote: > Naoki, > > Intel is planning open-source SVML library (most of them if it not 100%), 6 functions of SVML are open sourced for GCC and LLVM already. But, Intel SVML

Hi , Created new thread . Environment: Bare Metal server + CentOs with qemu/KVM +libvirt for virtualization Guest Instantiated with virt-install with forced CPU model like below virt-install --virt-type kvm --name compute-0 --cpu Haswell,+fma,+movbe,+fsgsbase,+bmi1,+hle,+avx2,+smep,+bmi2,+erms,+invpcid,+rtm --ram=61440 --vcpus=20 --os-type=linux --os-variant=generic After guest installation

> Am 11.05.2017 um 16:29 schrieb Leon Fauster <leonfauster at googlemail.com>: > >> Am 11.05.2017 um 14:48 schrieb Leon Fauster <leonfauster at googlemail.com>: >> >> https://access.redhat.com/support/policy/intel >> >> shows mainly Xeon CPUs. What about >> >> Intel Core i7-6700 Quad-Core Skylake >> >> has the current EL6

Hi, I'm running libvert on a Debian 7 system. I have upgraded libvert and qemu from source (v1.06 and 1.5.0 respectively) and the problem persists. The guest OS is also a Debian 7 system running a non-SMP kernel. The error message from virt-manager is Error starting domain: unsupported configuration: guest and host CPU are not compatible: Host CPU does not provide required features: rtm,

I have this code, which works fine on MacOS and Linux hosts: const char *target_specific_cpu_args; const char *target_specific_features; if (g->is_native_target) { target_specific_cpu_args = ZigLLVMGetHostCPUName(); target_specific_features = ZigLLVMGetNativeFeatures(); } else { target_specific_cpu_args = ""; target_specific_features =

I'm looking at the instruction formats and I can't grok the comments. For example: // SSSE3 Instruction Templates: // // SS38I - SSSE3 instructions with T8 prefix. // SS3AI - SSSE3 instructions with TA prefix. // Where are these prefix names coming from? I can't find any mention of them in the Intel literature. Also, there's this curious table: // Prefix byte classes

hello , thanks for comments . I tried now with force options for CPU flag which were not supported . Now the command with non fully supported CPU model gets executed , But i am surprised to see that still Guest cpu model is not changed and still same as host cpu model(SAndy Bridge) Why don't i see the model as HAswell now , could you please comment. Command used : virt-install

On Mar 23, 2009, at 12:57 PM, David A. Greene wrote: > I'm looking at the instruction formats and I can't grok the > comments. For > example: > > // SSSE3 Instruction Templates: > // > // SS38I - SSSE3 instructions with T8 prefix. > // SS3AI - SSSE3 instructions with TA prefix. > // > > Where are these prefix names coming from? I can't find any

This drop-in patch increases the performance of the get_checksum1() function on x86-64. On the target slow CPU performance of the function increased by nearly 50% in the x86-64 default SSE2 mode, and by nearly 100% if the compiler was told to enable SSSE3 support. The increase was over 200% on the fastest CPU tested in SSSE3 mode. Transfer time improvement with large files existing on both ends

The newly-released kernel v2.6.32-504.23.4.el6 includes the back-ported SHA256-SSSE3 driver. Why is the generic version of the SHA256 driver selected at runtime instead of the SSSE3 version on this x86_64 system? Yes, my CPU does support the SSSE3 instruction set, and the use of SHA256 is invoked by the LUKS "cipher=aes-cbc-essiv:sha256" option. On the running system I see that the

rkotler at mipsswbrd006-le:~/caviumllvm/build/test$ make Making LLVM 'lit.site.cfg' file... Making LLVM unittest 'lit.site.cfg' file... ( ulimit -t 600 ; ulimit -d 512000 ; ulimit -m 512000 ; ulimit -s 8192 ; \ /usr/bin/python /home/rkotler/workspace/llvm/utils/lit/lit.py -s -v . ) XPASS: LLVM :: tools/llvm-cov/llvm-cov.test (8916 of 9784) ******************** TEST

What do you base this on? Per https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html : "For the x86-32 compiler, you must use -march=cpu-type, -msse or -msse2 switches to enable SSE extensions and make this option effective. For the x86-64 compiler, these extensions are enabled by default." That reads to me like we're fine for SSE2. As stated in my comments, SSSE3 support must be

I suspect that there are 2 issues here: * I have incorrect alignment somewhere * MSVC / .pdb / CodeView debugging is not working correctly. I think the latter would help solve the former. I will send out a new email later talking about the issues I'm having debugging llvm-generated binaries with MSVC. On Sat, Sep 30, 2017 at 3:33 PM, Andrew Kelley <superjoe30 at gmail.com> wrote:

I just did a yum update on a CentOS 7 / Xen 4.6 server which took me from kernel-3.18.34-20.el7.x86_64 -> kernel-3.18.44-20.el7.x86_64 After rebooting, the following notice is printed immediately upon xl create'ing a domain: libxl: notice: libxl_numa.c:499:libxl__get_numa_candidate: NUMA placement failed, performance might be affected Indeed performance is significantly degraded. This