similar to: [GlobalISel] Predicated TImmLeafs in patterns

On Wed, May 8, 2013 at 1:48 PM, Nadav Rotem <nrotem at apple.com> wrote: > > On May 8, 2013, at 12:51 PM, Eric Christopher <echristo at gmail.com> wrote: > > On Wed, May 8, 2013 at 11:32 AM, Nadav Rotem <nrotem at apple.com> wrote: > > > On May 8, 2013, at 11:07 AM, dag at cray.com wrote: > > It might be as simple as adding > an IR-level predicated

On Wed, May 8, 2013 at 3:31 PM, Nadav Rotem <nrotem at apple.com> wrote: > > On May 8, 2013, at 1:59 PM, Eric Christopher <echristo at gmail.com> wrote: > > I can almost see that, but how is the intrinsic any different from a > conservative width for stores/loads where they're not handled by an > optimization pass? I'm assuming I'm missing something here.

On May 10, 2013, at 11:53 AM, dag at cray.com wrote: > Jeff Bush <jeffbush001 at gmail.com> writes: > >> Ah, I think I get it now. This was mentioned earlier in the thread, >> but it didn't click at the time. It sounds like I can do instruction >> selection with a pattern like (omitting selection of the sources): >> >> let Constraints = "$dst

On Wed, May 8, 2013 at 11:32 AM, Nadav Rotem <nrotem at apple.com> wrote: >...we do need support for masked load/stores, and > I think that we should implement them as target independent intrinsics. As I understand, one of the tricks for converting to SSA form in LLVM is to make all variable references be loads/stores, then use Mem2Reg to convert those back to registers. It seems

Hi, I was wondering what would be the best way to lower a select operation two predicated movs. I looked through the ARM, MIPS, and NVPTX backends and they all seem to lower a select to some sort of conditional move or native select operation. Ex. select t3, cond, t2, t1 Becomes cond mov t3, t2 !cond mov t3, t1 -Dilan -------------- next part -------------- An HTML attachment was scrubbed...

http://bugzilla.mindrot.org/show_bug.cgi?id=1273 Summary: Interactive mode detection should not be predicated on pty allocation Product: Portable OpenSSH Version: v4.5p1 Platform: Other OS/Version: All Status: NEW Severity: normal Priority: P2 Component: sftp-server AssignedTo:

https://bugzilla.mindrot.org/show_bug.cgi?id=1273 Tim Connors <tim.w.connors at gmail.com> changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |tim.w.connors at gmail.com --- Comment #6 from Tim Connors <tim.w.connors at gmail.com> 2011-10-10

On May 8, 2013, at 1:59 PM, Eric Christopher <echristo at gmail.com> wrote: > I can almost see that, but how is the intrinsic any different from a > conservative width for stores/loads where they're not handled by an > optimization pass? I'm assuming I'm missing something here. > > -eric I don't understand what you mean by "conservative width".

Ohh, that makes sense. And is the reason the first instruction doesn't get deleted because the ExpandPseudoInstructions pass occurs after Register Allocation and machine dead code elimination? -Dilan On Fri, Jul 7, 2017 at 12:37 PM Friedman, Eli <efriedma at codeaurora.org> wrote: > On 7/7/2017 12:10 PM, Dilan Manatunga wrote: > > My bad for not looking further. I'm still

On Wed, May 8, 2013 at 11:32 AM, Nadav Rotem <nrotem at apple.com> wrote: > > On May 8, 2013, at 11:07 AM, dag at cray.com wrote: > > It might be as simple as adding > an IR-level predicated load and predicated store, I'm not sure. > > > I think that selects on the inputs+outputs of instructions is a good > abstraction, and I don't think that we need to

My bad for not looking further. I'm still somewhat confused though. MOVCCr gets expanded in the ARMExpandPseudoInsts pass, and it still seems only a case of one instruction replacing the other. My worry of emitting two instructions, is that a dead code pass will eliminate the first instruction cause it thinks the second instruction is defining the same register. -Dilan On Fri, Jul 7, 2017

On 4/10/2013 12:45 PM, Hal Finkel wrote: > > Should AnalyzeBranch be enhanced to somehow indicate conditional returns? I don't think that returns can ever be analyzable (since LLVM's CFG does not have a designated exit block). > Alternatively, the diamond conversion routine contains this: > > // RemoveExtraEdges won't work if the block has an unanalyzable branch,

> I'm not sure I understand the full impact of this example, and I would like to. > > What are the desired memory model semantics for a masked store? Specifically, let me suppose a simplified vector model of <2 x i64> on an i64-word-size platform. > Hi Chandler, I brought the example in this email thread to show that the optimizations that we currently have won't

On Fri, May 10, 2013 at 9:53 AM, <dag at cray.com> wrote: > Jeff Bush <jeffbush001 at gmail.com> writes: > >> Ah, I think I get it now. This was mentioned earlier in the thread, >> but it didn't click at the time. It sounds like I can do instruction >> selection with a pattern like (omitting selection of the sources): >> >> let Constraints =

On Thu, May 9, 2013 at 1:09 AM, Nadav Rotem <nrotem at apple.com> wrote: > On May 8, 2013, at 4:00 PM, Eric Christopher <echristo at gmail.com> wrote: > > > Thinking that a masked store is conservatively a store of the full > width of the store right? > > > It depends on the optimization. Consider this example: > > masked_store(Val, Ptr , M) > X =

I've inherited some target code, but there is no SELECT lowering in my target. But somewhere/somehow SELECT is being transformed into a predicated move. I've traced SELECT everywhere in Codegen/SelectionDAG. Any ideas on tracking this down to the point in Codegen lowering/dag-conversion to a predicated series? Again, I do not have a lowering rule in my target for SELECT. If I do a IR

On Thu, May 9, 2013 at 7:47 AM, <dag at cray.com> wrote: > Chandler Carruth <chandlerc at google.com> writes: > > > What are the desired memory model semantics for a masked store? > > Specifically, let me suppose a simplified vector model of <2 x i64> on > > an i64-word-size platform. > > > > masked_store(<42, 42>, Ptr, <true,

On Thu, May 9, 2013 at 6:04 PM, <dag at cray.com> wrote: > Dan Gohman <dan433584 at gmail.com> writes: > > > But I don't understand why defining this as not being a data race > > would complicate things. I'm assuming the mask values are > > statically known. Can you explain a bit more? > > > > It's an interesting question

Ah, I think I get it now. This was mentioned earlier in the thread, but it didn't click at the time. It sounds like I can do instruction selection with a pattern like (omitting selection of the sources): let Constraints = "$dst = $oldvalue" in { def MASKEDARITH : MyInstruction< (outs VectorReg:$dst), (ins MaskReg:$mask, VectorReg:$src1, VectorReg:$src2,

On May 8, 2013, at 12:51 PM, Eric Christopher <echristo at gmail.com> wrote: > On Wed, May 8, 2013 at 11:32 AM, Nadav Rotem <nrotem at apple.com> wrote: >> >> On May 8, 2013, at 11:07 AM, dag at cray.com wrote: >> >> It might be as simple as adding >> an IR-level predicated load and predicated store, I'm not sure. >> >> >> I