similar to: [PATCH 05/70] x86/insn: Make inat-tables.c suitable for pre-decompression code

Displaying 20 results from an estimated 600 matches similar to: "[PATCH 05/70] x86/insn: Make inat-tables.c suitable for pre-decompression code"

2020 Apr 17
0
[PATCH 05/70] x86/insn: Make inat-tables.c suitable for pre-decompression code
On Fri, Apr 17, 2020 at 09:50:00PM +0900, Masami Hiramatsu wrote: > On Thu, 16 Apr 2020 17:24:06 +0200 > Joerg Roedel <joro at 8bytes.org> wrote: > Ah, I got it. So you intended to port the instruction decoder to > pre-decompression boot code, correct? Right, it is needed there to decode instructions which cause #VC exceptions when running as an SEV-ES guest. > > The
2020 May 12
0
[PATCH v3 23/75] x86/boot/compressed/64: Setup GHCB Based VC Exception handler
On Tue, May 12, 2020 at 08:11:57PM +0200, Borislav Petkov wrote: > > +# sev-es.c inludes generated $(objtree)/arch/x86/lib/inat-tables.c > > "includes" > > > +CFLAGS_sev-es.o += -I$(objtree)/arch/x86/lib/ > > Does it? > > I see > > #include "../../lib/inat.c" > #include "../../lib/insn.c" > > only and with
2020 May 12
2
[PATCH v3 23/75] x86/boot/compressed/64: Setup GHCB Based VC Exception handler
On Tue, Apr 28, 2020 at 05:16:33PM +0200, Joerg Roedel wrote: > From: Joerg Roedel <jroedel at suse.de> > > Install an exception handler for #VC exception that uses a GHCB. Also > add the infrastructure for handling different exit-codes by decoding > the instruction that caused the exception and error handling. > > Signed-off-by: Joerg Roedel <jroedel at suse.de>
2020 May 12
2
[PATCH v3 23/75] x86/boot/compressed/64: Setup GHCB Based VC Exception handler
On Tue, Apr 28, 2020 at 05:16:33PM +0200, Joerg Roedel wrote: > From: Joerg Roedel <jroedel at suse.de> > > Install an exception handler for #VC exception that uses a GHCB. Also > add the infrastructure for handling different exit-codes by decoding > the instruction that caused the exception and error handling. > > Signed-off-by: Joerg Roedel <jroedel at suse.de>
2020 Apr 28
0
[PATCH v3 23/75] x86/boot/compressed/64: Setup GHCB Based VC Exception handler
From: Joerg Roedel <jroedel at suse.de> Install an exception handler for #VC exception that uses a GHCB. Also add the infrastructure for handling different exit-codes by decoding the instruction that caused the exception and error handling. Signed-off-by: Joerg Roedel <jroedel at suse.de> --- arch/x86/Kconfig | 1 + arch/x86/boot/compressed/Makefile
2011 Aug 10
1
xtable - caption missing with float=FALSE
Hi, For some reason I'm finding that my table caption is disappearing if I print xtable output with the floating argument set to FALSE. Below is a very simple Sweave file that produces two tables the first has no caption and the second has a caption (if you want to see it http://www.zevross.com/temp/test.pdf). Does anyone know what I can do to fix this? Zev (I'm using Windows 7, 64
2020 Feb 11
0
[PATCH 18/62] x86/boot/compressed/64: Setup GHCB Based VC Exception handler
From: Joerg Roedel <jroedel at suse.de> Install an exception handler for #VC exception that uses a GHCB. Also add the infrastructure for handling different exit-codes by decoding the instruction that caused the exception and error handling. Signed-off-by: Joerg Roedel <jroedel at suse.de> --- arch/x86/Kconfig | 1 + arch/x86/boot/compressed/idt_64.c
2014 Aug 04
3
[LLVMdev] LLVM AllocaInst and StoreInst
Hi, I am trying to write a simple interpreter. I am trying to generate LLVM IR for assignment operation. The code for the generation part looks like this llvm::Value* codeGenSymTab(llvm::LLVMContext& context) { > printf("\n CodeGen SymTab \n"); > Value *num = ConstantInt::get(Type::getInt64Ty(context), aTable.value, > true); > Value *alloc = new
2004 Oct 23
0
Re: FXTable -- numColumns & resize
On Fri, 22 Oct 2004 13:39:06 -0700, Bob Sidebotham <bob@windsong.bc.ca> wrote: > In 1.2 FXTable, numColumns is documented as numCols, but should be > numColumns, I think. Also the examples/table.rb app uses numCols, and > should use numColumns. Yes, you''re right. I''ve added both of these bugs to the FXRuby bug list, found here:
2011 Jul 31
1
Character encode
Good evening guys, I''m using now with 3 rails web app themes rails to generate the layouts, almosteverything working ok, only the names I write code in such a ride when I put atable in the header with character "รง" character shows the strange but data thatcomes from the database shows normal, which can be and how can I fix? Thank you all ... -- Alcelyo R Mariz Bacharel em
2007 Jun 04
2
RMySQL question, sql with R vector or list
Hi, I am trying to write a RMySQL sql script inside R such that part of the SQL would be R list or vector. For example, I want to select * from Atable where ID would equal to a members of R list or vector of "1, 2, 3". Here the ID list was generated inside R and then try to feed to mysql to call to get additional data sets. Can someone on the list help? Thanks. -- Waverley @ Palo
2006 Jul 10
0
ajax scaffold problem
Hi, I am using ajax_scaffold to generate against a model backed by atable on SQLServer... It creates all the stuff, and I can list the items in my table... But, the "Edit" and "Create New" buttons dont work... The strange thing is that the problem occurs when I edit the ajax_scaffold generated controller with before_filter/set_charset... I try to set the charset of pages
2004 Nov 29
2
Interesting oopses...
OK - this is starting to get frustrating... Are there any known issues with 2.6.9 and traffic shaping? I am using 2.6.9 with geoip 20041115, and get odd oopses. The following script oopses my box: ----------------------------------------------------- #!/bin/sh -x IFOUT=''eth1'' IFIN=''eth0'' TC=''/sbin/tc''
2012 Aug 07
0
[LLVMdev] [RFC] Hexagon insn table refactoring
We are working on enabling the MC code-emitter for Hexagon and it's necessary to add the missing opcode bits to the insn tables. I'm considering scooping the opcode bits from the processor source files for correctness' and expediency's sake and I'm afraid that a significant refactoring of the current insn tables will be necessary. I intend to create classes for each insn
2019 Feb 28
0
Regression with "arm64: KVM: Skip MMIO insn after emulation" on 4.4 stable
On Wed, Feb 27, 2019 at 04:36:39PM -0800, Daniel Verkamp wrote: > Hello, > > In my testing of crosvm[1] with Linux 4.4.175, I am observing failures > on a 'kevin' Chromebook (RK3399) device - the guest kernel does not > even get to the point of printing its first messages, and the host > seems to be spinning at 100% CPU in KVM_RUN. > > I narrowed this down to the
2020 Apr 28
0
[PATCH v3 10/75] x86/insn: Add insn_rep_prefix() helper
From: Joerg Roedel <jroedel at suse.de> Add a function to check whether an instruction has a REP prefix. Signed-off-by: Joerg Roedel <jroedel at suse.de> --- arch/x86/include/asm/insn-eval.h | 1 + arch/x86/lib/insn-eval.c | 24 ++++++++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/arch/x86/include/asm/insn-eval.h b/arch/x86/include/asm/insn-eval.h index
2019 Feb 28
0
Regression with "arm64: KVM: Skip MMIO insn after emulation" on 4.4 stable
On 28/02/2019 08:49, Marc Zyngier wrote: > On Thu, 28 Feb 2019 08:16:05 +0000, > Greg KH <gregkh at linuxfoundation.org> wrote: > > Hi both, > >> >> On Wed, Feb 27, 2019 at 04:36:39PM -0800, Daniel Verkamp wrote: >>> Hello, >>> >>> In my testing of crosvm[1] with Linux 4.4.175, I am observing failures >>> on a 'kevin'
2012 Aug 14
0
[LLVMdev] [RFC] Hexagon insn table refactoring
Since Jakob had expressed some concerns regarding machine-generated files, I asked him by email about his views on this RFC. Here are the emails that we exchanged in attach. Anyone feel free to jump in via the mailing-list. TIA -- Evandro Menezes Austin, TX emenezes at codeaurora.org Qualcomm Innovation Center, Inc is a member of the Code Aurora Forum -------------- next
2009 Sep 10
0
[PATCH 01/13] nv50: extend insn src mask function
Extend its usage to avoiding e.g. emission of negation instructions in tx_insn for sources we don't need. --- src/gallium/drivers/nv50/nv50_program.c | 118 +++++++++++++++++++------------ 1 files changed, 72 insertions(+), 46 deletions(-) diff --git a/src/gallium/drivers/nv50/nv50_program.c b/src/gallium/drivers/nv50/nv50_program.c index 4a83852..a6c70ae 100644 ---
2019 Feb 28
2
Regression with "arm64: KVM: Skip MMIO insn after emulation" on 4.4 stable
Hello, In my testing of crosvm[1] with Linux 4.4.175, I am observing failures on a 'kevin' Chromebook (RK3399) device - the guest kernel does not even get to the point of printing its first messages, and the host seems to be spinning at 100% CPU in KVM_RUN. I narrowed this down to the 4.4 stable backport of "arm64: KVM: Skip MMIO insn after emulation" - with this patch