similar to: [PATCH 02/10] x86/cpufeature: Kill cpu_has_hypervisor

We try to handle the hypervisor compatibility mode by detecting hypervisor through a specific order. This is not robust, since hypervisors may implement each others features. This patch tries to handle this situation by always choosing the last one in the CPUID leaves. This is done by letting .detect() returns a priority instead of true/false and just re-using the CPUID leaf where the signature

We try to handle the hypervisor compatibility mode by detecting hypervisor through a specific order. This is not robust, since hypervisors may implement each others features. This patch tries to handle this situation by always choosing the last one in the CPUID leaves. This is done by letting .detect() returns a priority instead of true/false and just re-using the CPUID leaf where the signature

We try to handle the hypervisor compatibility mode by detecting hypervisor through a specific order. This is not robust, since hypervisors may implement each others features. This patch tries to handle this situation by always choosing the last one in the CPUID leaves. This is done by letting .detect() returns a priority instead of true/false and just re-using the CPUID leaf where the signature

I'll be interested in seeing the improvements. As a reference, this is what I get in an Intel 6700K when I compare gcc 5.4 (Ofast flto) vs published Intel results. 23x in libquantum, and over 40% in many benchmarks. I think that it is mostly from AoS vs SoA and loop transformations. 5.4

Hi Tobias- The loop fusion you mention is the one in libquantum/cpu2006 ? Or something else in cpu2017 ? -Thx Dibyendu -----Original Message----- From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of Tobias Grosser via llvm-dev Sent: Wednesday, August 16, 2017 10:10 AM To: renau at uncore.io; llvm-dev at lists.llvm.org Subject: Re: [llvm-dev] Heroic LLVM optimizations Hi

I am a professor at UC Santa Cruz, but I also do consulting a Huawei. Chris Lattner told me that I should post this in the llvm-dev. HiSilicon (Santa Clara office) is looking for some developer capable of implementing the "heroic optimizations" (http://llvm.org/devmtg/2015-10/slides/Gerolf-PerformanceImprovementsAndHeadroom.pdf) in LLVM. Focus on SPEC2006 but also looking at the

From: Borislav Petkov <bp at suse.de> Using static_cpu_has() is pointless on those paths, convert them to the boot_cpu_has() variant. No functional changes. Reported-by: Nadav Amit <nadav.amit at gmail.com> Signed-off-by: Borislav Petkov <bp at suse.de> Cc: Aubrey Li <aubrey.li at intel.com> Cc: Dave Hansen <dave.hansen at intel.com> Cc: Dominik Brodowski <linux

With the x86 instruction emulator no pretty complete, I''d like to re-submit this patch to support cmpxchg16b on x86-64 and at once rename the underlying emulator callback function pointer (making clear that if implemented, it is to operate on two longs rather than two 32-bit values). At the same time it fixes an apparently wrong emulator context initialization in the shadow code.

This follows Linux commit 39fe05e58c5e448601ce46e6b03900d5bf31c4b0, noticing that all this setup is pointless when ARAT support is there, and knowing that on SLED11''s native kernel it has actually caused S3 resume issues. A question would be whether HPET legacy interrupts should be forced off in this case (rather than leaving whatever came from firmware). Signed-off-by: Jan Beulich

These are known to not support the feature, so we can save ourselves from emitting the resulting #GP fault recovery related message (which might worry people looking at the logs). Signed-off-by: Jan Beulich <jbeulich@suse.com> --- a/xen/arch/x86/cpu/intel.c +++ b/xen/arch/x86/cpu/intel.c @@ -204,7 +204,7 @@ static void __devinit init_intel(struct detect_ht(c); } - if

On 03/19/2014 06:07 AM, Paolo Bonzini wrote: > Il 19/03/2014 04:15, Waiman Long ha scritto: >>>> You should see the same values with the PV ticketlock. It is not clear >>>> to me if this testing did include that variant of locks? >>> >>> Yes, PV is fine. But up to this point of the series, we are concerned >>> about spinlock performance when

On 03/19/2014 06:07 AM, Paolo Bonzini wrote: > Il 19/03/2014 04:15, Waiman Long ha scritto: >>>> You should see the same values with the PV ticketlock. It is not clear >>>> to me if this testing did include that variant of locks? >>> >>> Yes, PV is fine. But up to this point of the series, we are concerned >>> about spinlock performance when

From 291adaf4ad6174c5641a7239c1801373e92e9975 Mon Sep 17 00:00:00 2001 From: Liu Jinsong <jinsong.liu@intel.com> Date: Thu, 28 Nov 2013 05:26:06 +0800 Subject: [PATCH v4 3/7] X86: MPX IA32_BNDCFGS msr handle When MPX supported, a new guest-state field for IA32_BNDCFGS is added to the VMCS. In addition, two new controls are added: - a VM-exit control called "clear BNDCFGS" - a

X86: implement PCID/INVPCID for hvm This patch handle PCID/INVPCID for hvm: For hap hvm, we enable PCID/INVPCID, since no need to intercept INVPCID, and we just set INVPCID non-root behavior as running natively; For shadow hvm, we disable PCID/INVPCID, otherwise we need to emulate INVPCID at vmm by setting INVPCID non-root behavior as vmexit. Signed-off-by: Liu, Jinsong

On Fri, Feb 14, 2020 at 12:05:32PM +0800, Jason Wang wrote: > > The standard driver model is a 'bus' driver provides the HW access > > (think PCI level things), and a 'hw driver' attaches to the bus > > device, > > This is not true, kernel had already had plenty virtual bus where virtual > devices and drivers could be attached, besides mdev and virtio,

CPUID level 0x00000007:0 (ebx) is word 9, instead of word 7. ... make it consistent with native Linux. Signed-off-by: Li Xin <xin.li@intel.com> diff -r d7c755c25bb9 xen/include/asm-x86/cpufeature.h --- a/xen/include/asm-x86/cpufeature.h Sat May 28 08:58:08 2011 +0100 +++ b/xen/include/asm-x86/cpufeature.h Tue May 31 07:34:34 2011 +0800 @@ -142,7 +142,7 @@ #define X86_FEATURE_TOPOEXT

(Applies cleanly only on top of the previously sent SVM/LBR patch.) Signed-off-by: Jan Beulich <jbeulich@novell.com> Index: 2007-08-08/xen/arch/x86/hvm/svm/svm.c =================================================================== --- 2007-08-08.orig/xen/arch/x86/hvm/svm/svm.c 2007-08-08 11:40:11.000000000 +0200 +++ 2007-08-08/xen/arch/x86/hvm/svm/svm.c 2007-08-08 11:43:53.000000000 +0200

2014-05-07 11:01-0400, Waiman Long: > From: Peter Zijlstra <peterz at infradead.org> > > Because the qspinlock needs to touch a second cacheline; add a pending > bit and allow a single in-word spinner before we punt to the second > cacheline. I think there is an unwanted scenario on virtual machines: 1) VCPU sets the pending bit and start spinning. 2) Pending VCPU gets

2014-05-07 11:01-0400, Waiman Long: > From: Peter Zijlstra <peterz at infradead.org> > > Because the qspinlock needs to touch a second cacheline; add a pending > bit and allow a single in-word spinner before we punt to the second > cacheline. I think there is an unwanted scenario on virtual machines: 1) VCPU sets the pending bit and start spinning. 2) Pending VCPU gets

qemu recently added support for 3dnow instructions. Because of that, 3dnow will be featured among cpuid bits. But this will break kvm in cpus that don't have those instructions (which includes my laptop). So we fixup our cpuid before exposing it to the guest. Signed-off-by: Glauber Costa <gcosta at redhat.com> --- arch/x86/kvm/x86.c | 22 ++++++++++++++++++----