Displaying 20 results from an estimated 300 matches similar to: "[Bug 111217] New: compilation of vdpau shaders crashes in handleCVT_CVT"
2015 Nov 25
4
NV50 compute support questions
Hi,
On 20-11-15 17:07, Samuel Pitoiset wrote:
>
>
> On 11/20/2015 11:36 AM, Hans de Goede wrote:
>> Hi Samual, et al,
>
> Hi Hans,
>
>>
>> In
>> http://cgit.freedesktop.org/mesa/mesa/commit/src/gallium/drivers/nouveau?id=ff72440b40211326eda118232fabd53965410afd
>>
>> you write: "This compute support has been tested by
>> Pierre
2015 Nov 20
4
NV50 compute support questions
Hi Samual, et al,
In http://cgit.freedesktop.org/mesa/mesa/commit/src/gallium/drivers/nouveau?id=ff72440b40211326eda118232fabd53965410afd
you write: "This compute support has been tested by
Pierre Moreau and myself with some compute kernels."
Can you provide testing instructions (and the
necessary files) so that I can try to reproduce
your tests ?
And once I've reproduced your
2015 Nov 26
2
NV50 compute support questions
Hi,
On 26-11-15 09:42, Samuel Pitoiset wrote:
> Well, if you remove that assert locally, all compute tests in src/gallium/tests/trivial/compute.c pass on GK106, except the atomic ones.
Do you mean the:
Assertion `pres->target != PIPE_BUFFER' failed.
or the:
Assertion `tex->defExists(0) && tex->srcExists(0)' failed.
assert? Or is the first one not present for
2019 Jul 18
3
[Bug 111167] New: Dividing zero by a uniform in loop header causes segfault in nv50_ir::NVC0LegalizeSSA::handleDIV
https://bugs.freedesktop.org/show_bug.cgi?id=111167
Bug ID: 111167
Summary: Dividing zero by a uniform in loop header causes
segfault in nv50_ir::NVC0LegalizeSSA::handleDIV
Product: Mesa
Version: git
Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
Severity: minor
2015 Feb 20
10
[PATCH 01/11] nvc0/ir: add emission of dadd/dmul/dmad opcodes, fix minmax
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
.../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 66 +++++++++++++++++++++-
1 file changed, 63 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index dfb093c..e38a3b8 100644
---
2019 Jul 25
9
[Bug 111218] New: Segmentation fault in nv50_ir::NVC0LegalizeSSA::handleDIV when dividing result of textureSize
https://bugs.freedesktop.org/show_bug.cgi?id=111218
Bug ID: 111218
Summary: Segmentation fault in
nv50_ir::NVC0LegalizeSSA::handleDIV when dividing
result of textureSize
Product: Mesa
Version: 19.0
Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
Severity: major
2017 Apr 03
5
[PATCH v2 0/3] nv50/ir: Preapre for running Opts inside a loop
Slowly we are getting to the point, that we miss enough optimization
opportunities as the result of our own passes.
For this we need to fix AlgebraicOpt to be able to handle mods on sources
without creating new issues.
The last patch enables looping opts.
v2: update commit author
Karol Herbst (3):
nv50/ir: fix AlgebraicOpt for slcts with mods
nv50/ir: handle logops with NOT in AlgebraicOpt
2017 Apr 03
3
[PATCH 0/3] nv50/ir: Preapre for running Opts inside a loop
Slowly we are getting to the point, that we miss enough optimization
opportunities as the result of our own passes.
For this we need to fix AlgebraicOpt to be able to handle mods on sources
without creating new issues.
The last patch enables looping opts.
Karol Herbst (3):
nv50/ir: fix AlgebraicOpt for slcts with mods
nv50/ir: handle logops with NOT in AlgebraicOpt
nv50/ir: run some
2017 Jun 11
14
[RFC 0/9] Add precise/invariant semantics to TGSI
Running Tomb Raider on Nouveau I found some flicker caused by ignoring precise
modifiers on variables inside Nouveau.
This series add precise/invariant handling to TGSI, which can be then used by
drivers to disable certain unsafe optimisations which may otherwise alter
calculations, which depend on having the same result across shaders.
This series fixes this bug in Tomb Raider and one CTS test
2015 Aug 19
5
[PATCH 1/2] nvc0/ir: detect AND/SHR pairs and convert into EXTBF
Some shaders appear to extract bits using shift/and combos. Detect
(some) of those and convert to EXTBF instead.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
.../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 66 +++++++++++++++-------
1 file changed, 46 insertions(+), 20 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
2016 Mar 17
4
[PATCH mesa v2 1/2] nouveau: codegen: Use FILE_MEMORY_BUFFER for buffers
Some of the lowering steps we currently do for FILE_MEMORY_GLOBAL only
apply to buffers, making it impossible to use FILE_MEMORY_GLOBAL for
OpenCL global buffers.
This commits changes the buffer code to use FILE_MEMORY_BUFFER at the
ir_from_tgsi and lowering steps, freeing use of FILE_MEMORY_GLOBAL
for use with OpenCL global buffers.
Note that after lowering buffer accesses use the
2017 Nov 14
2
[RFC PATCH] nouveau/compiler: Allow to omit line numbers when printing instructions
This comes in handy when checking "NV50_PROG_DEBUG=1" outputs with diff!
Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de>
---
src/gallium/drivers/nouveau/codegen/nv50_ir.cpp | 6 +++---
src/gallium/drivers/nouveau/codegen/nv50_ir.h | 2 +-
src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h | 1 +
2016 Apr 08
2
[PATCH mesa v2 1/2] nouveau: codegen: Use FILE_MEMORY_BUFFER for buffers
Hi,
On 23-03-16 23:10, Samuel Pitoiset wrote:
> Are you sure this won't break compute shaders on fermi?
> Could you please double-check that?
I just checked:
lspci:
01:00.0 VGA compatible controller: NVIDIA Corporation GF119 [GeForce GT 610] (rev a1)
Before this patch-set:
[hans at plank piglit]$ ./piglit run -o shader -t '.*arb_shader_storage_buffer_object.*' results/shader
2017 Jul 31
1
[RFC PATCH] nv50/ir: allow spilling of def values for constrained MERGES/UNIONS
This lets us spill more values and compile a big shader for Civilization 6.
Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de>
---
src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp | 2 --
1 file changed, 2 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
index b33d7b4010..f29c8a1a95
2016 Mar 16
13
[PATCH mesa 1/6] tgsi_build: Fix return of uninitialized memory in tgsi_*_instruction_memory
tgsi_default_instruction_memory / tgsi_build_instruction_memory were
returning uninitialized memory for tgsi_instruction_memory.Texture and
tgsi_instruction_memory.Format. Note 0 means not set, and thus is a
correct default initializer for these.
Fixes: 3243b6fc97 ("tgsi: add Texture and Format to tgsi_instruction_memory")
Cc: Nicolai Hähnle <nicolai.haehnle at amd.com>
2017 Jun 10
1
[Bug 101371] New: GlobalCSE Pass moves phi instructions
https://bugs.freedesktop.org/show_bug.cgi?id=101371
Bug ID: 101371
Summary: GlobalCSE Pass moves phi instructions
Product: Mesa
Version: git
Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
Severity: normal
Priority: medium
Component: Drivers/DRI/nouveau
Assignee: nouveau
2014 Jul 08
1
[PATCH] nv50/ir: use unordered_set instead of list to keep our instructions in uses
This shortens runtime of piglit test fp-long-alu to ~22s
No piglit regressions observed on nvc0!
Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de>
---
src/gallium/drivers/nouveau/codegen/nv50_ir.cpp | 6 +++---
src/gallium/drivers/nouveau/codegen/nv50_ir.h | 7 ++++---
src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 2 +-
2017 Nov 17
2
[PATCH v2] nouveau/compiler: Allow to omit line numbers when printing instructions
This comes in handy when checking "NV50_PROG_DEBUG=1" outputs with diff!
V2:
- Use environmental variable (Karol Herbst)
Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de>
---
src/gallium/drivers/nouveau/codegen/nv50_ir.cpp | 6 +++---
src/gallium/drivers/nouveau/codegen/nv50_ir.h | 2 +-
2016 Mar 16
2
[PATCH mesa 4/6] nouveau: codegen: s/FILE_MEMORY_GLOBAL/FILE_MEMORY_BUFFER/
This approach leads to the emitters needing to know about both global and
buffer, even though at that point, they are identical. I was thinking that
in the lowering logic, buffer would just get rewritten as global (with the
offset added), thus not needing any change to the emitters. What do you
think about such an approach?
On Mar 16, 2016 2:24 AM, "Hans de Goede" <hdegoede at
2016 Mar 14
2
[RFC mesa] nouveau: Add support for OpenCL global memory buffers
This little "hack" fixes the use of OpenCL global memory buffers with
nouveau, but clearly the #if 0 is not a solution as it breaks buffers
with GLSL.
The reason I'm posting this as an RFC patch is to discuss how to solve
this properly, 2 solutions come to mind:
1) Use separate nv50_ir::FILE_MEMORY_xxx values for buffers versus
TGSI_FILE_MEMORY with TGSI_MEMORY_TYPE_GLOBAL,