similar to: [PATCH] drm/nouveau/fb/ramgk104: fix spelling mistake "sucessfully" -> "successfully"

this is my first patch on the list through git send-mail and I hope everything is set up right, sorry for the noise here, but I don't want to try with an empty mail :) as the subject already says, this patch fixes one of the more serious issues while reclocking gddr5 on kepler cards. It works for me and for a bunch of others I met on IRC. Karol Herbst (1): pll/gk104: fix PLL instability

Explicitly declare constants are unsigned long to address the following sparse warnings: warning: constant is so big it is long Signed-off-by: Wambui Karuga <wambui.karugax at gmail.com> --- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf108.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c | 2 +-

Explicitly declare constants as unsigned long long to address the following sparse warnings: warning: constant is so big it is long v2: convert to unsigned long long for compatibility with 32-bit architectures. Signed-off-by: Wambui Karuga <wambui.karugax at gmail.com> Suggested by: lia Mirkin <imirkin at alum.mit.edu> --- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c | 2 +-

Probably want ULL for 32-bit arches to be correct here too. On Tue, Dec 31, 2019 at 3:53 PM Wambui Karuga <wambui.karugax at gmail.com> wrote: > > Explicitly declare constants are unsigned long to address the following > sparse warnings: > warning: constant is so big it is long > > Signed-off-by: Wambui Karuga <wambui.karugax at gmail.com> > --- >

"hiding" unconditional assignments in the if() parentesis makes for hard to read code and has no advantage over placing these assignments in proper formated lines before the if() statement. Simply move those lines out. Before sending out roughly 20 patches to fix the roughly 50 cases - all in the nouveau driver. I would like to know if this will be accepted at all. Signed-off-by:

Fixes regression introduced in commit 70790f4f "drm/nouveau/clock: pull in the implementation from all over the place" When code was moved from nv50_crtc_set_clock to nvc0_clock_pll_set, the PLLs it is used for got limited to only the first two VPLLs. nv50_crtc_set_clock was only called to change VPLLs, so it didn't limit what it was used for in any way. Since nvc0_clock_pll_set is

I've splitted my big series between the part which actually fixes the engine reclocking bits and the part handling voltage/clock updates on temperature change, so that the more reviewed parts can be merged in faster. This series fixes a lot of Engine reclocking issues found on Fermi, Kepler and all Maxwell generation GPUs. It does _not_ fix memory reclocking on Fermi. It mostly contains of

In bulletpoints: - Add some support for G94 and G96 reclocking. Has been tested on literally two cards, which is hardly adequate as "full coverage". On the other hand, the changes were small enough to make me confident this might work for others as well. - Fix NV50 wait for VBLANK when no monitor is plugged in. - Voltage related inprovements for GT21x. - Slightly improve Keplers

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- drm/nouveau/nvkm/engine/gr/ctxgk20a.c | 2 +- drm/nouveau/nvkm/subdev/fb/ramgk104.c | 8 ++++---- drm/nouveau/nvkm/subdev/therm/nv40.c | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drm/nouveau/nvkm/engine/gr/ctxgk20a.c b/drm/nouveau/nvkm/engine/gr/ctxgk20a.c index ddaa16a..ad0a6cf 100644 ---

I am a little unsure about the change in nouveau_fence, maybe somebody with more knowledge about the code can look into it? Signed-off-by: Karol Herbst <karolherbst at gmail.com> --- drm/nouveau/dispnv04/arb.c | 6 ++---- drm/nouveau/nouveau_fence.c | 2 -- drm/nouveau/nvkm/subdev/fb/ramgk104.c | 4 +--- 3 files changed, 3 insertions(+), 9 deletions(-) diff --git

Hello, Attached a small patch that correctly identifies the DLLoff bit for >=GF100. Marked RFC because I haven't seen any GDDR5 samples that *enable* the DLL. I'd like to verify whether the DLL should be reset when enabled. Could increase likelihood of succesfull reclock. Ben: could you do some experiments with this bit to see if GDDR5 needs some DLL reset logic? Thanks, and happy

Parts are re-used even on NVA3, others from GF100 on Signed-off-by: Roy Spliet <nouveau at spliet.org> --- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h | 17 +++ drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c | 92 +++++++++----- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c | 140 +--------------------- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c | 61 ++++++++++ 4

No, no, these will not implement Fermi reclocking. This set of patches contains some of the preparatory work that I deem stable enough to move upstream. Notable changes - Training pattern upload routines from GK104+ now shared with GT215+ - Timing calculation for Fermi - GDDR5 MR calculation from VBIOS timing table v1.0. Also useful for that pesky GT 240. - A routine to translate a VBIOS init

On 11/06/2014 13:59, Roy Spliet wrote: > Dear Mr. Dew, > > I hereby wish to propose the X.org EVoC project "REclock - > Reverse-engineer and implement NVA3/5/8 Voltage- and Frequency Scaling > in Nouveau" for which I am willing to participate, and apply for the > associated funding. Full details below or on > http://nouveau.spliet.org/evoc.html . For any further

https://bugs.freedesktop.org/show_bug.cgi?id=91523 Bug ID: 91523 Summary: [NVE7] driver cannot initialize gpu(failed to parse ramcfg data) Product: xorg Version: unspecified Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Severity: blocker Priority: medium

Hi again, I got a new dmesg log with the debug parameters, but I guess I could not isolate VESA. I blacklisted it at /etc/modprobe.d/blacklist.conf but comparing those logs I see no difference... Is it possible to isolate VESA somehow without removing it? The new logs are here, I'm posting full content because I'm not sure what information is more relevant...

Two patches went missing as a result of PEBCAK. No v2 marks as nothing changed really. Just resending for easier enforcement of patch order in other people's trees. Sorry for the noise. Original message: No, no, these will not implement Fermi reclocking. This set of patches contains some of the preparatory work that I deem stable enough to move upstream. Notable changes - Training pattern

I have looked at problem with Fermi GPUs where changing to higher clock led to really bad perfomance (with GpuTest 20x worse perfomance) and later also crashes of the nouveau. It seemed to be affected by Shader Clock in Voltage Entries in the video BIOS. Disabling BYPASS_PLL_CHECK in CLK0_CTRL seems to completely fix the issue. I have tried to search this BYPASS_PLL_CHECK in Nvidia traces but

Resend of patch #7 to fix behaviour when failing to pause parts of the GPU

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 I think we are getting close to a "gold" release here. - - added MacModel support for the mini - - fixed Xv crasher - - lots of LVDS fixes - - external tmds should work again (assuming the external chip is bios inited) Alex Deucher (13): RADEON: round 3 on the PLLs. should fix the LVDS issues RADEON: fix up dvo support (still