Displaying 20 results from an estimated 200 matches similar to: "[Bug 109876] New: JIYE BHUTTO"
2013 Apr 28
2
unsupported url scheme
fileUrl <- "https://data.baltimorecity.gov/api/views/dz54-2aru/rows.csv?accessType=DOWNLOAD"download.file(fileUrl,destfile="./data/Cameras.csv",method="curl") I tried it after installing package "RCurl" but it give error message: Error in download.file(fileUrl, destfile = "Cameras.csv") :
unsupported URL schemeI can you help me to solve this
2014 Dec 13
2
[LLVMdev] Vectorization factor limitation in Loop Vectorizer
So IMO, if we modify the VF calculation for targets/subtargets using TTI where higher VF is supported
The vectorizer’s scope will become wider.
Did/do you foresee any issue with this?
Thanks,
Shahid
From: Nadav Rotem [mailto:nrotem at apple.com]
Sent: Saturday, December 13, 2014 2:47 AM
To: Shahid, Asghar-ahmad
Cc: llvmdev at cs.uiuc.edu
Subject: Re: [LLVMdev] Vectorization factor limitation in
2008 Apr 22
3
Parsing incoming extension till first @
Hi All
When I dial a number it reaches the asterisk switch as abc at xyz@123.com
what I need to do is to parse the abc and send it to my pstn gateway
as in
exten => _.,2,Dial(SIP/${EXTEN}@pstn.gw)
this does work but I do have a varying number of numbers before the @
exten => _.,1,Dial(SIP/${EXTEN:0:12}@pstn.gw)
Well can I use some kind of regular expression to take all numbers
before
2015 May 04
2
[LLVMdev] [RFC][PATCH] Adding absd/hadd/sad intrinsics
Hi Asghar-Ahmed,
I saw your last ping - sorry, I'm away on vacation and back on Wednesday.
Generally, I'm not sure that having both absd/hadd and sad are compatible
with the discussions going on in other threads, for example my thread about
min and max.
Given that those two intrinsics are fairly trivial to match , I don't see
the need to have two different canonical forms.
James
On
2015 May 04
2
[LLVMdev] Load value and broadcast in LLVM
Hi Shahid,
Thank you so much for your response. You suggested approach is what I am
right now using. However, it seems that the overhead is a little bit high
because we are introducing two more instructions. I was wondering if there
was a cheaper way to do it.
Best,
Zhi
On Mon, May 4, 2015 at 2:12 AM, Shahid, Asghar-ahmad <
Asghar-ahmad.Shahid at amd.com> wrote:
> Hi Zhi,
>
>
2014 Dec 11
2
[LLVMdev] Vectorization factor limitation in Loop Vectorizer
Hi Nadav/Devs
I am exploring Loop Vectorizer to vectorize i8 scalar operations into 8xi8 vector operation.
I was expecting the Loop Vectorizer to analyze the profitability for vectorization factor(VF) of 8,
However it is not doing so due to the widest type calculation done for the blocks inside the loop.
May be I am missing something, however, I am curious to know why Loop Vectorizer limits the
2015 May 05
2
[LLVMdev] [RFC][PATCH] Adding absd/hadd/sad intrinsics
On 4 May 2015 at 08:37, Shahid, Asghar-ahmad
<Asghar-ahmad.Shahid at amd.com> wrote:
> My worry is regarding the query for cost calculation for specific SAD
> instructions such as ‘psad’ (X86) or ‘usad’ (ARM) in Loop Vectorizer.
Hi Shahid,
The vectorizer's cost model has the ability to return different costs
for the same instruction based on the arguments (scalar/vector,
2015 May 06
2
[LLVMdev] [RFC][PATCH] Adding absd/hadd/sad intrinsics
> For the time being, if you can get away with heuristics, and that fills your
> allocated time for this task, that it's the best way forward for now.
Sorry that I could not get what exactly you mean with "heuristics".
Is it the "intrinsics approach" itself or something else?
BTW, now my plan is to just add the two intrinsics for 'absolute difference'
and
2016 May 12
3
sum elements in the vector
> why in order to add this particular instruction (sum elements in a vector) I need to add an insrinsic?
Adding intrinsic is not the only way, it is one of the way and user WILL-NOT be required to invoke
It specifically.
Currently LLVM does not have any instruction to directly represent “sum of elements in a vector” and
generate your particular instruction.However, you can do it without
2015 May 06
2
[LLVMdev] [RFC][PATCH] Adding absd/hadd/sad intrinsics
Hi Renato,
That’s right. I agree with your *pattern vs complexity* thinking.
So I would drop llvm.sad() and go ahead with the remaining two.
Does it make sense in general?
Regards,
Shahid
> -----Original Message-----
> From: Renato Golin [mailto:renato.golin at linaro.org]
> Sent: Tuesday, May 05, 2015 8:40 PM
> To: Shahid, Asghar-ahmad
> Cc: James Molloy; llvmdev at
2016 May 16
4
sum elements in the vector
This would be really cool. We have several instructions that perform horizontal vector operations, and have to use built-ins to select them as there is no easy way of expressing them in a TD file. Some like SUM for a ‘v4i32’ are easy enough to express with a pattern fragment, SUM ‘v8i16’ takes TableGen a long time to compute, but SUM ‘v16i8’ resulted in TableGen disappearing into itself for
2016 May 16
0
sum elements in the vector
I'm starting to think we should directly implement horizontal operations on
vector types.
My suspicion is that coming up with a nice model for this would help us a
lot with things like:
- Idiom recognition of reduction patterns that use horizontal arithmetic
- Ability to use horizontal operations in SLPVectorizer
- Significantly easier cost modeling of vectorizing loops with reductions
in
2015 Nov 19
5
[RFC] Introducing a vector reduction add instruction.
After some attempt to implement reduce-add in LLVM, I found out a
easier way to detect reduce-add without introducing new IR operations.
The basic idea is annotating phi node instead of add (so that it is
easier to handle other reduction operations). In PHINode class, we can
add a flag indicating if the phi node is a reduction one (the flag can
be set in loop vectorizer for vectorized phi nodes).
2007 Aug 30
1
Fwd: Priotirize SSH Traffic
oops, i forgot to reply to the list :-/
Début du message réexpédié :
> De : Vincent Dautremont <vdautrem@ulb.ac.be>
> Date : 30 août 2007 16:58:26 GMT+02:00
> À : Ali Jawad <alijawad1@gmail.com>
> Objet : Rép : [LARTC] Priotirize SSH Traffic
>
> try that
> #tc qdisc add dev eth0 root handle1: prio
> # tc filter add dev eth0 protocol ip parent 1: prio 1 u32
2006 Aug 24
3
Help On Upload Limiting Using CBQ.init
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
Hi Guys
Ive got an internet cafe on which I have a debian sarge box running.
The Debian box acts as a gateway and it has masquerading on. I have 40
client PC and i do not want to assign more than 64k per pc for upload
and the same is true for download too. Ive done alot of research and Ive
read tutorials about CBQ and HTB. I found that CBQ.init is
2016 Apr 04
7
sum elements in the vector
My target has an instruction that adds up all elements in the vector and
stores the result in a register. I'm trying to implement it in my compiler
but I'm not sure even where to start.
I did look at other targets, but they don't seem to have anything like it (
I could be wrong. My experience with LLVM is limited, so if I missed it,
I'd appreciate if someone could point it out ).
2015 May 01
2
[LLVMdev] [RFC][PATCH] Adding absd/hadd/sad intrinsics
Hi All,
I would like to introduce intrinsics to generate efficient codes for 'absolute differences', 'horizontal add'
and 'sum of absolute differences' Idioms used by user programs.
Identifying these idioms at lower level (Codegen) is complex. These idioms can be identified in LV/SLP
and vectorized using above intrinsics to generate better code.
Proposal:
1. Add
2015 Apr 18
2
[LLVMdev] how can I create an SSE instrinsics sqrt?
Thanks, Shahid. It is fixed now.
On Fri, Apr 17, 2015 at 8:50 PM, Shahid, Asghar-ahmad <
Asghar-ahmad.Shahid at amd.com> wrote:
> Hi zhi,
>
>
>
> You have to also pass the value type to getDecalaration() API such as
>
>
>
> Value* sqrtv = Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_sqrt_pd,
> v->getType());
>
>
>
> Regards,
>
>
2015 May 05
1
[LLVMdev] [RFC][PATCH] Adding absd/hadd/sad intrinsics
Hi Renato,
Thanks for your response. My concern was actually this. For example, take vector type V8i16 on X86 target
With llvm.sad() intrinsic:
VC1 (Vector Cost) = Cost associated with "PSAD" instruction.
W/ llvm.absd() and llvm.hadd()
VC2 = Cost associated with "absolute diff" + "horizontal add" ( ??? )
As I will be querying with getIntrinsicCost(ID) for these
2016 May 28
4
sum elements in the vector
Hi Rail,
Below 2 revisions might be of your interest which Detect SAD patterns and
emit psadbw instructions on X86.:
http://reviews.llvm.org/D14840
http://reviews.llvm.org/D14897
Intrinsics related to absdiff revisons :
http://reviews.llvm.org/D10867
http://reviews.llvm.org/D11678
Hope this helps.
Regards,
Suyog
On Sat, May 28, 2016 at 4:20 AM, Rail Shafigulin via llvm-dev <
llvm-dev at