similar to: [PATCH 0/1] drm/nouveau/disp: prefer identity-mapped route of SOR <-> macro link

Taken from NVIDIA binary driver (Linux 64-bit, revision 390.25) from README.txt. Signed-off-by: Danilo Krummrich <danilokrummrich at dk-develop.de> --- drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c | 41 ++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c index

Taken from NVIDIA binary driver (Linux 64-bit, revision 390.25) from README.txt. Signed-off-by: Danilo Krummrich <danilokrummrich at dk-develop.de> --- drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c | 41 ++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c index

Signed-off-by: Lyude Paul <lyude at redhat.com> --- drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c index 6094805fbd63..06b19883a06b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c +++

With DCB 4.1 implemented by VBIOS since GM20x GPUs, SOR crossbar routing should be possible, such that any SOR sublink can drive any macro link. Unfortunately, there's at least one card where some SOR sublinks being connected to a particular macro link are causing failures. To work around this issue, supply a quirk for such cards which prevents a dynamic mapping of SOR sublink and macro link

With DCB 4.1 implemented by VBIOS since GM20x GPUs, SOR crossbar routing should be possible, such that any SOR sublink can drive any macro link. Unfortunately, there's at least one card where some SOR sublinks being connected to a particular macro link are causing failures. To work around this issue, supply a quirk for such cards which prevents a dynamic mapping of SOR sublink and macro link

This is the beginnings of HDMI 2.0 support. All of the "extra" features are left out, such as 12/16bpc, YUV420, etc. I've verified that with this code, a GP108 (GT1030) can switch between 4k at 60 and 1920x1080 at 60 on a LG 4K TV. Further, I've verified via i2c tools, that the SCDC writes really do happen. I suspect that the patch for keeping track of the high-speed TMDS

Now that we're supporting things like Ada and the GSP, there's situations where we really need to actually know the display state that we're starting with when loading the driver in order to prevent breaking GSP expectations. The first step in doing this is making it so that we can read the current state of IORs from nvkm in DRM, so that we can fill in said into into the atomic state.

Turns out we made a silly mistake when coming up with OR inheritance on nouveau. On pre-DCB 4.1, iors are statically routed to output paths via the DCB. On later generations iors are only routed to an output path if they're actually being used. Unfortunately, it appears with NVIF_OUTP_INHERIT_V0 we make the mistake of assuming the later is true on all generations, which is currently leading us

On 2018-02-05 02:39, Ben Skeggs wrote: > On 5 February 2018 at 11:37, Ben Skeggs <skeggsb at gmail.com> wrote: >> On 5 February 2018 at 11:22, Danilo Krummrich >> <danilokrummrich at dk-develop.de> wrote: >>> On Gainward GTX 1070 routing any other SOR than SOR-1 to macro link >>> 'G' (outp index 7) causes failures: >>> >>> [

On 5 February 2018 at 11:22, Danilo Krummrich <danilokrummrich at dk-develop.de> wrote: > On Gainward GTX 1070 routing any other SOR than SOR-1 to macro link > 'G' (outp index 7) causes failures: > > [ 6.712111] nouveau 0000:01:00.0: bus: MMIO read of 00000000 FAULT at 61c880 [ IBUS ] > [ 6.724888] nouveau 0000:01:00.0: disp: intr24 80000000 > [ 8.716668]

Currently we use the drm_dp_dpcd_read_caps() helper in the DRM side of nouveau in order to read the DPCD of a DP connector, which makes sure we do the right thing and also check for extended DPCD caps. However, it turns out we're not currently doing this on the nvkm side since we don't have access to the drm_dp_aux structure there - which means that the DRM side of the driver and the NVKM

More arrays (and arguments) for dcpd were set to 16, when it looks like DP_RECEIVER_CAP_SIZE (15) should be used. Fix the remaining cases, seen with GCC 13: ../drivers/gpu/drm/nouveau/nvif/outp.c: In function 'nvif_outp_acquire_dp': ../include/linux/fortify-string.h:57:33: warning: array subscript 'unsigned char[16][0]' is partly outside array bounds of 'u8[15]' {aka

Not entirely sure why this never came up when I originally tested this (maybe some BIOSes already have this setup?) but the ->caps_init vfunc appears to cause the display engine to throw an exception on driver init, at least on my ThinkPad P72: nouveau 0000:01:00.0: disp: chid 0 mthd 008c data 00000000 0000508c 0000102b This is magic nvidia speak for "You need to have the DMA notifier

From: Ben Skeggs <bskeggs at redhat.com> [ Upstream commit a1ef8bad506e4ffa0c57ac5f8cb99ab5cbc3b1fc ] This is a SOR register, and not indexed by the bound head. Fixes display not coming up on high-bandwidth HDMI displays under a number of configurations. Signed-off-by: Ben Skeggs <bskeggs at redhat.com> Signed-off-by: Sasha Levin <sashal at kernel.org> ---

From: Ben Skeggs <bskeggs at redhat.com> [ Upstream commit a1ef8bad506e4ffa0c57ac5f8cb99ab5cbc3b1fc ] This is a SOR register, and not indexed by the bound head. Fixes display not coming up on high-bandwidth HDMI displays under a number of configurations. Signed-off-by: Ben Skeggs <bskeggs at redhat.com> Signed-off-by: Sasha Levin <sashal at kernel.org> ---

Greetings, box: bog standard [tc]rusty old Nvidia equipped Q6600 Medion (Aldi) deskside kernel: master.today (v4.12-11690-gccd5d1b91f22) lspci -nn -d 10de: 01:00.0 VGA compatible controller [0300]: NVIDIA Corporation G84 [GeForce 8600 GT] [10de:0402] (rev a1) abreviated dmesg: ... [ 3.720990] fb: switching to nouveaufb from VESA VGA [ 3.744489] Console: switching to colour dummy device

These didn't apply cleanly to v5.8, so here's a backported version. Lyude Paul (2): drm/nouveau/kms/nv50-: Program notifier offset before requesting disp caps drm/nouveau/kms/nv50-: Log SOR/PIOR caps drivers/gpu/drm/nouveau/dispnv50/core507d.c | 25 ++++++++++++++++----- drivers/gpu/drm/nouveau/dispnv50/disp.c | 10 +++++++++ 2 files changed, 29 insertions(+), 6 deletions(-)

On Tue, Nov 3, 2015 at 7:02 PM, Ben Skeggs <skeggsb at gmail.com> wrote: > On 11/04/2015 08:41 AM, Ilia Mirkin wrote: >> From: Hauke Mehrtens <hauke at hauke-m.de> >> >> Without this patch a pixel clock rate above 165 MHz on a TMDS link is >> assumed to be dual link. This is true for DVI, but not for HDMI. HDMI >> supports no dual link, but it supports

From: Hauke Mehrtens <hauke at hauke-m.de> Without this patch a pixel clock rate above 165 MHz on a TMDS link is assumed to be dual link. This is true for DVI, but not for HDMI. HDMI supports no dual link, but it supports pixel clock rates above 165 MHz. Only activate Dual Link mode when it is actual possible. Signed-off-by: Hauke Mehrtens <hauke at hauke-m.de> Signed-off-by: Ilia

The values are already stored on chipset specific basis in the ctor. Make the most of them and simplify the code further by using a temporary variable to avoid code duplication. Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com> --- Found this patch laying around in a local branch. While the it does not reduce the number of lines, I believe that it makes the code is alot more