similar to: [PATCH] gm107/ir: use lane 0 for manual textureGrad handling

Displaying 19 results from an estimated 19 matches similar to: "[PATCH] gm107/ir: use lane 0 for manual textureGrad handling"

2017 Dec 20
0
[PATCH] gm107/ir: use lane 0 for manual textureGrad handling
On Tue, Dec 19, 2017 at 11:41 PM, Ilia Mirkin <imirkin at alum.mit.edu> wrote: > This is parallel to the pre-SM50 change which does this. Adjusts the > shuffles / quadops to make the values correct relative to lane 0, and > then splat the results to all lanes for the final move into the target > register. > > Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> >
2014 Jul 05
1
[PATCH 1/2] nvc0/ir: use manual TXD when offsets are involved
Something about how we're implementing offsets for TXD is wrong, just flip to the generic quadop-based implementation in that case. This is the minimal fix appropriate for backporting. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> Cc: <mesa-stable at lists.freedesktop.org> --- src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 3 ++- 1 file changed, 2
2012 Dec 04
5
[LLVMdev] Proposal: Adding aligned instruction bundle support to MC
Hello, We (the Portable Native Client team) would like to start upstreaming our LLVM modifications which contain support for Software Fault Isolation (SFI) as required for sandboxing programs to run under Native Client. Since the "total patch size" is quite big, we are splitting the effort to manageable chunks that can be committed, tested and reviewed separately as independently as
2012 Dec 05
0
[LLVMdev] Proposal: Adding aligned instruction bundle support to MC
Hi Eli, > we are splitting the effort to manageable chunks that can > be committed, tested and reviewed separately as > independently as feasible I'd be interested in experimenting with this stuff sooner than later. Could you dump all the patches in a publicly accessible repo? How about Github? Thanks, Greg On Tue, Dec 4, 2012 at 3:53 PM, Eli Bendersky <eliben at
2012 Dec 05
2
[LLVMdev] Proposal: Adding aligned instruction bundle support to MC
Hi Greg, Our repos are public already, hosted on the Chromium infrastructure. Our builds are based out of the Native Client repository. The nacl git mirror is at http://git.chromium.org/native_client/src/native_client.git (no gitweb, sorry). That repo has pointers to a bunch of other repos which make pnacl (LLVM, clang, binutils, and a few others. see the file pnacl/DEPS for more). But if you just
2012 Dec 06
0
[LLVMdev] Proposal: Adding aligned instruction bundle support to MC
Hi Eli, How will these bundles interact with ARM codegen? The constant island pass in particular. -Jim On Dec 4, 2012, at 3:53 PM, Eli Bendersky <eliben at google.com> wrote: > Hello, > > We (the Portable Native Client team) would like to start upstreaming > our LLVM modifications which contain support for Software Fault > Isolation (SFI) as required for sandboxing
2012 Dec 06
0
[LLVMdev] Proposal: Adding aligned instruction bundle support to MC
> But if you just want to see the code and the diff against upstream... If others are interested as well, here's all your changes via Github's "compare" feature:
2014 Jul 05
0
[PATCH] nvc0: do quadops on the right texture coordinates for TXD
handleTEX moves the layer as the first argument. This makes sure that the quadops deal with the texture coordinates. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> Cc: <mesa-stable at lists.freedesktop.org> --- src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git
2014 Sep 26
0
[PATCH] gm107/ir: take relative pfetch offset into account
There is no dedicated instruction for this, so just combine it with the constant offset. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> Cc: "10.3" <mesa-stable at lists.freedesktop.org> --- This fixes the spec/glsl-1.50/execution/geometry/dynamic_input_array_index piglit test. src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp | 5 ++++- 1 file changed,
2014 May 13
1
[PATCH 1/2] nv50/ir: make sure that texprep/texquerylod's args get coalesced
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> Cc: "10.2" <mesa-stable at lists.freedesktop.org> --- Not 100% sure of the significance of this code, but this seems like the correct thing to do... will definitely run it through a full piglit run before pushing out. src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git
2014 Sep 25
0
[PATCH] gm107/ir: fix texture argument order
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> Cc: "10.3" <mesa-stable at lists.freedesktop.org> --- With this, all the tex-miplevel-selection tests pass on maxwell. There is a minor bit of this change which affects textureGrad on kepler that I have yet to test, but I'm moderately sure it's correct and was only working by luck before. (Changing the insbf to use
2014 Aug 08
2
[PATCH 1/3] nvc0/ir: add base tex offset for fermi indirect tex case
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- .../drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp index f010767..4a9e48f 100644 ---
2018 Sep 23
3
[Bug 108032] New: nv50_ir_lowering_gm107.cpp:326: undefined reference to `nv50_ir::NVC0LoweringPass::loadMsAdjInfo32(nv50_ir::TexInstruction::Target, unsigned int, int, nv50_ir::Value*, bool)'
https://bugs.freedesktop.org/show_bug.cgi?id=108032 Bug ID: 108032 Summary: nv50_ir_lowering_gm107.cpp:326: undefined reference to `nv50_ir::NVC0LoweringPass::loadMsAdjInfo32(nv50_ir::T exInstruction::Target, unsigned int, int, nv50_ir::Value*, bool)' Product: Mesa Version: git
2014 May 18
1
[PATCH 1/2] nv50/ir: fix s32 x s32 -> high s32 multiply logic
Retrieving the high 32 bits of a signed multiply is rather annoying. It appears that the simplest way to do this is to compute the absolute value of the arguments, and perform a u32 x u32 -> u64 operation. If the arguments' signs differ, then negate the result. Since there is no u64 support in the cvt instruction, we have the perform the 2's complement negation "by hand".
2014 Apr 18
0
[PATCH] nouveau/codegen: add missing values for OP_TXLQ into the target arrays
Also rework things so that if someone were to add an opcode without adjusting the values in these arrays, there will be a compilation error. This fixes a few quadop-related piglit regressions since commit d5faf8e78603. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp | 12 +++++++-----
2015 Feb 20
10
[PATCH 01/11] nvc0/ir: add emission of dadd/dmul/dmad opcodes, fix minmax
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- .../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 66 +++++++++++++++++++++- 1 file changed, 63 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp index dfb093c..e38a3b8 100644 ---
2017 Nov 11
0
Wine release 2.21
The Wine development release 2.21 is now available. What's new in this release (see below for details): - Still more metafile support in GdiPlus. - Indirect draws support in Direct 3D. - Calling convention fixes on ARM. - Improved serial port detection on Linux. - Services fixes on WoW64. - Better DPI scaling in the Shell Explorer. - Various bug fixes. The source is available
2017 Jun 11
14
[RFC 0/9] Add precise/invariant semantics to TGSI
Running Tomb Raider on Nouveau I found some flicker caused by ignoring precise modifiers on variables inside Nouveau. This series add precise/invariant handling to TGSI, which can be then used by drivers to disable certain unsafe optimisations which may otherwise alter calculations, which depend on having the same result across shaders. This series fixes this bug in Tomb Raider and one CTS test
2015 Jun 07
43
[Bug 90887] New: PhiMovesPass in register allocator broken
https://bugs.freedesktop.org/show_bug.cgi?id=90887 Bug ID: 90887 Summary: PhiMovesPass in register allocator broken Product: Mesa Version: git Hardware: All OS: All Status: NEW Severity: normal Priority: medium Component: Drivers/DRI/nouveau Assignee: nouveau at