similar to: [PATCH] disp/nv50-: bump max chans to 21

Just like how the P50 will occasionally leave the disp's core channel on before nouveau starts initializing, it will occasionally do the same thing with the rest of the dmac channel in addition to the core channel. Example: [ 1.604375] nouveau 0000:01:00.0: disp: outp 04:0006:0f81: no heads (0 3 4) [ 1.604858] nouveau 0000:01:00.0: disp: outp 04:0006:0f81: aux power -> always [

From: Colin Ian King <colin.king at canonical.com> The constant values being shifted are 32 bit integers and may potentially overflow on the shift. Avoid this potential overflow by making them unsigned long long values before the shift. Detected by CoverityScan, CID#1469383, 1469400 ("Unintentional integer overflow") Signed-off-by: Colin Ian King <colin.king at

Hello Ben Skeggs, The patch a9c44a88ca2f: "drm/nouveau/disp/nv50-: add channel interfaces to control error interrupts" from May 8, 2018, leads to the following static checker warning: drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c:169 nv50_disp_chan_intr() warn: should '65537 << chan->chid.user' be a 64 bit type?

Hello Ben Skeggs, The patch a9c44a88ca2f: "drm/nouveau/disp/nv50-: add channel interfaces to control error interrupts" from May 8, 2018, leads to the following static checker warning: drivers/gpu/drm/nouveau/nvkm/engine/disp/changf119.c:55 gf119_disp_chan_intr() warn: should '1 << chan->chid.user' be a 64 bit type?

Not entirely sure why this never came up when I originally tested this (maybe some BIOSes already have this setup?) but the ->caps_init vfunc appears to cause the display engine to throw an exception on driver init, at least on my ThinkPad P72: nouveau 0000:01:00.0: disp: chid 0 mthd 008c data 00000000 0000508c 0000102b This is magic nvidia speak for "You need to have the DMA notifier

The gv100_disp_wimm is not declared, so make it static to avoid the following warning: drivers/gpu/drm/nouveau/nvkm/engine/disp/wimmgv100.c:39:1: warning: symbol 'gv100_disp_wimm' was not declared. Should it be static? Signed-off-by: Ben Dooks <ben.dooks at codethink.co.uk> --- drivers/gpu/drm/nouveau/nvkm/engine/disp/wimmgv100.c | 2 +- 1 file changed, 1 insertion(+), 1

From: Ben Skeggs <bskeggs at redhat.com> [ Upstream commit 0e6176c6d286316e9431b4f695940cfac4ffe6c2 ] The implementations for most channel types contains a map of methods to priv registers in order to provide debugging info when a disp exception has been raised. This info is missing from the implementation of PIO channels as they're rather simplistic already, however, if an exception

From: Ben Skeggs <bskeggs at redhat.com> [ Upstream commit 0e6176c6d286316e9431b4f695940cfac4ffe6c2 ] The implementations for most channel types contains a map of methods to priv registers in order to provide debugging info when a disp exception has been raised. This info is missing from the implementation of PIO channels as they're rather simplistic already, however, if an exception

From: Ben Skeggs <bskeggs at redhat.com> [ Upstream commit 0e6176c6d286316e9431b4f695940cfac4ffe6c2 ] The implementations for most channel types contains a map of methods to priv registers in order to provide debugging info when a disp exception has been raised. This info is missing from the implementation of PIO channels as they're rather simplistic already, however, if an exception

From: Ben Skeggs <bskeggs at redhat.com> [ Upstream commit 0e6176c6d286316e9431b4f695940cfac4ffe6c2 ] The implementations for most channel types contains a map of methods to priv registers in order to provide debugging info when a disp exception has been raised. This info is missing from the implementation of PIO channels as they're rather simplistic already, however, if an exception

From: Ben Skeggs <bskeggs at redhat.com> [ Upstream commit 0e6176c6d286316e9431b4f695940cfac4ffe6c2 ] The implementations for most channel types contains a map of methods to priv registers in order to provide debugging info when a disp exception has been raised. This info is missing from the implementation of PIO channels as they're rather simplistic already, however, if an exception

From: Ben Skeggs <bskeggs at redhat.com> [ Upstream commit 0e6176c6d286316e9431b4f695940cfac4ffe6c2 ] The implementations for most channel types contains a map of methods to priv registers in order to provide debugging info when a disp exception has been raised. This info is missing from the implementation of PIO channels as they're rather simplistic already, however, if an exception

Not entirely sure why this never came up when I originally tested this (maybe some BIOSes already have this setup?) but the ->caps_init vfunc appears to cause the display engine to throw an exception on driver init, at least on my ThinkPad P72: nouveau 0000:01:00.0: disp: chid 0 mthd 008c data 00000000 0000508c 0000102b This is magic nvidia speak for "You need to have the DMA notifier

On Tue, 2020-08-25 at 08:28 +1000, Ben Skeggs wrote: > On Tue, 25 Aug 2020 at 04:33, Lyude Paul <lyude at redhat.com> wrote: > > Not entirely sure why this never came up when I originally tested this > > (maybe some BIOSes already have this setup?) but the ->caps_init vfunc > > appears to cause the display engine to throw an exception on driver > > init, at

Not entirely sure why this never came up when I originally tested this (maybe some BIOSes already have this setup?) but the ->caps_init vfunc appears to cause the display engine to throw an exception on driver init, at least on my ThinkPad P72: nouveau 0000:01:00.0: disp: chid 0 mthd 008c data 00000000 0000508c 0000102b This is magic nvidia speak for "You need to have the DMA notifier

We were returning PTR_ERR() on a NULL pointer, which obviously won't work. nvkm_engine_ref() will return an error in case something went wrong. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> Reported-by: Dan Carpenter <dan.carpenter at oracle.com> --- drm/nouveau/nvkm/subdev/secboot/gp102.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git

Hello Alexandre Courbot, The patch 5429f82f3415: "drm/nouveau/secboot: add gp102/gp104/gp106/gp107 support" from Jan 26, 2017, leads to the following static checker warning: drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c:63 gp102_run_secure_scrub() warn: passing zero to 'PTR_ERR' drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c 46 static int 47

GR is similar to GP100, with a few unavailable registers. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drm/nouveau/include/nvkm/engine/gr.h | 1 + drm/nouveau/nvkm/engine/gr/Kbuild | 1 + drm/nouveau/nvkm/engine/gr/gf100.h | 4 +++ drm/nouveau/nvkm/engine/gr/gp100.c | 13 ++++++-- drm/nouveau/nvkm/engine/gr/gp102.c | 1 + drm/nouveau/nvkm/engine/gr/gp10b.c |

Not entirely sure why this never came up when I originally tested this (maybe some BIOSes already have this setup?) but the ->caps_init vfunc appears to cause the display engine to throw an exception on driver init, at least on my ThinkPad P72: nouveau 0000:01:00.0: disp: chid 0 mthd 008c data 00000000 0000508c 0000102b This is magic nvidia speak for "You need to have the DMA notifier

Not entirely sure why this never came up when I originally tested this (maybe some BIOSes already have this setup?) but the ->caps_init vfunc appears to cause the display engine to throw an exception on driver init, at least on my ThinkPad P72: nouveau 0000:01:00.0: disp: chid 0 mthd 008c data 00000000 0000508c 0000102b This is magic nvidia speak for "You need to have the DMA notifier