similar to: Fermi+ shader header docs

On Thu, May 21, 2015 at 10:05 AM, Robert Morell <rmorell at nvidia.com> wrote: > Hi Ilia, > > On Sat, May 02, 2015 at 12:34:21PM -0400, Ilia Mirkin wrote: >> Hi, >> >> As I'm looking to add some support to nouveau for features like atomic >> counters and images, I'm running into some confusion about what the >> first word of the shader header

--- rnndb/display/nv3_pramdac.xml | 67 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/rnndb/display/nv3_pramdac.xml b/rnndb/display/nv3_pramdac.xml index 13b6a7b..e236921 100644 --- a/rnndb/display/nv3_pramdac.xml +++ b/rnndb/display/nv3_pramdac.xml @@ -79,12 +79,79 @@ <bitfield pos="28" name="VCLK_DB2"/> <bitfield

NV10TCL defines the vertex buffer registers both as arrays and as individual named registers. This causes duplicate register definitions and the individual registers are not used either by the DDX or by the Mesa driver. Francisco Jerez said to remove them all. Signed-off-by: Luca Barbieri <luca at luca-barbieri.com> --- renouveau.xml | 49

First some data errors I get with both nv20 exa and nv20 dri/mesa. 1. RT_FORMAT LINEAR + X8R8G8B8 Ch 1/5 Class 0x0597 Mthd 0x0208 Data 0x00800080:0x00000105 Ch 1/5 Class 0x0597 Mthd 0x0208 Data 0x01000100:0x00000105 LINEAR + A8R8G8B8 Ch 1/5 Class 0x0597 Mthd 0x0208 Data 0x01000100:0x00000108 Ch 1/5 Class 0x0597 Mthd 0x0208 Data 0x00800080:0x00000108 The only value I found in renouveau dump

On 25/08/2014 20:58, Christian Costa wrote: > --- > rnndb/memory/nvc0_pbfb.xml | 37 ++++++++++++++++++++++++++++++++++--- > 1 file changed, 34 insertions(+), 3 deletions(-) > > diff --git a/rnndb/memory/nvc0_pbfb.xml b/rnndb/memory/nvc0_pbfb.xml > index 500cea9..e006dbe 100644 > --- a/rnndb/memory/nvc0_pbfb.xml > +++ b/rnndb/memory/nvc0_pbfb.xml > @@ -49,23 +49,54 @@

Hi, I am looking at the effect of allelochemicals produced by two freshwater macrophyte species on two different algal species at different days. I am comparing the effect of each macrophyte on each algae at each day. I received help from someone doing the LMEM (Linear mixed-effect models) and he told me to do ANOVA to analyse the LMEM. However, I received these feedback from my examinor; 1. An

Hi, This series targets automatic boot menu generation, but most of it is the Lua upgrade, because I got tired reading deprecated API docs. It's mostly a straightforward forward port of the earlier Syslinux specific changes to Lua 5.1, except that: * I chose the add a stub getenv() implementation to the COM32 API instead of #ifdefing out all the references in Lua, and * I kept oslib

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- mrnuke on IRC reported that 3x 4K monitors (11520 width total) got rejected for some reason. I'm guessing it's this since a single giant FB has to be used. Not sure if the hardware will actually support it, but... who knows. drm/nouveau/nouveau_display.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git

Hi, I'm having an issue with subregisters on my target. With a pseudo that writes to a 32 bit reg: %vreg20<def> = toHi16_low0_pseudo %vreg2; reg32:%vreg20 hi16:%vreg2 expands to %vreg2<def> = COPY %a2h; hi16:%vreg2 %vreg43<def> = mov 0, pred:0, pred:%noreg, %ac0<imp-use>, %ac1<imp-use>; lo16:%vreg43 %vreg20<def> =

--- rnndb/memory/nvc0_pbfb.xml | 37 ++++++++++++++++++++++++++++++++++--- 1 file changed, 34 insertions(+), 3 deletions(-) diff --git a/rnndb/memory/nvc0_pbfb.xml b/rnndb/memory/nvc0_pbfb.xml index 500cea9..e006dbe 100644 --- a/rnndb/memory/nvc0_pbfb.xml +++ b/rnndb/memory/nvc0_pbfb.xml @@ -49,23 +49,54 @@ Most bitfields are unknown. </doc> <bitfield high="7"

This adds support for enabling automatic clockgating on nvidia GPUs for Fermi and later generations. This saves a little bit of power, bringing my fermi GPU's power consumption from ~28.3W on idle to ~27W, and my kepler's idle power consumption from ~23.6W to ~21.65W. Similar to how the nvidia driver seems to handle this, we enable clockgating for each engine that supports it after

Hello, I've recently come across an error reported by the GPU and would like to know what it means and especially what causes it to be triggered. Any information would be very useful: I'm seeing MP warp error 0x10 (appears in MP register 0x48). This is what we currently have in nouveau: <reg32 offset="0x048" name="TRAP_WARP_ERROR"> <!-- ctx-switched -->

Hi Lyude, thanks for the great work. Just a view comments inline. 2017-04-25 20:38 GMT+02:00 Lyude <lyude at redhat.com>: > This adds support for enabling automatic clockgating on nvidia GPUs for > Fermi and later generations. This saves a little bit of power, bringing > my fermi GPU's power consumption from ~28.3W on idle to ~27W, and my > kepler's idle power

Hi Ilia, On Fri, Oct 02, 2015 at 06:05:21PM -0400, Ilia Mirkin wrote: > Hi Robert, > > Thanks for the quick response! That goes in line with my observations > which is that these things happen when using an ATOM/RED instruction. > I've checked and rechecked that I'm generating ops with identical bits > as what the proprietary driver does, however (and nvdisasm prints

Thanks for the work so far. A quick scan through the first NVC4 trace at hand, using upstream demmio, reveals at least 20 writes to the BLCG registers of PGRAPH and a few in PXBAR prior to altering the value of register 0x20200 (see below). We know that these are related to the clock gating you enable. Are you 110% sure that fiddling with 0x20200 bits without first setting these values can

Hi Robert, Thanks for the quick response! That goes in line with my observations which is that these things happen when using an ATOM/RED instruction. I've checked and rechecked that I'm generating ops with identical bits as what the proprietary driver does, however (and nvdisasm prints identical output). Could you advise what the proper way of indicating that the memory is

On Wed, 2017-04-26 at 00:49 +0200, Karol Herbst wrote: > Hi Lyude, > > thanks for the great work. Just a view comments inline. > > 2017-04-25 20:38 GMT+02:00 Lyude <lyude at redhat.com>: > > This adds support for enabling automatic clockgating on nvidia GPUs > > for > > Fermi and later generations. This saves a little bit of power, > > bringing >

On Fri, Oct 9, 2020 at 5:54 PM Karol Herbst <kherbst at redhat.com> wrote: > > On Fri, Oct 9, 2020 at 11:35 PM Ondrej Zary <linux at zary.sk> wrote: > > > > Hello, > > I'm testing 5.9.0-rc8 and found that Riva TNT2 stopped working: > > [ 0.000000] Linux version 5.9.0-rc8+ (zary at gsql) (gcc (Debian 8.3.0-6) 8.3.0, GNU ld (GNU Binutils for Debian)

On Sat, Oct 10, 2020 at 12:23 AM Ilia Mirkin <imirkin at alum.mit.edu> wrote: > > On Fri, Oct 9, 2020 at 5:54 PM Karol Herbst <kherbst at redhat.com> wrote: > > > > On Fri, Oct 9, 2020 at 11:35 PM Ondrej Zary <linux at zary.sk> wrote: > > > > > > Hello, > > > I'm testing 5.9.0-rc8 and found that Riva TNT2 stopped working: > >

On Saturday 10 October 2020 02:02:42 Karol Herbst wrote: > On Sat, Oct 10, 2020 at 12:23 AM Ilia Mirkin <imirkin at alum.mit.edu> wrote: > > > > On Fri, Oct 9, 2020 at 5:54 PM Karol Herbst <kherbst at redhat.com> wrote: > > > > > > On Fri, Oct 9, 2020 at 11:35 PM Ondrej Zary <linux at zary.sk> wrote: > > > > > > > > Hello,