similar to: Fwd: [PATCH] D20841: TII: Add documentation about conditional exits. NFC

Hello! The if-converter tries to match 'Simple' patterns looking like this: // Simple (split, no rejoin): // EBB // | \_ // | | // | TBB---> exit // | // FBB The IfConverter::ValidSimple method (lib/CodeGen/IfConversion.cpp:461) checks if TBB matches this pattern. It basically does this by simply checking if AnalyseBranch fails on

Evan, et al., I've come across a small issue when using the if conversion pass in PPC to generate conditional returns. Here's a small example: ** Before if conversion ** BB#0: derived from LLVM BB %entry %R3<def> = LI 0 %CR0<def> = CMPLWI %R3, 0 BCC 68, %CR0, <BB#3> Successors according to CFG: BB#3(16) BB#1(16) BB#1: derived from LLVM BB

I am working on a back end for an architecture whose jump via table instruction includes the range check. If the index is out of range, the jump table instruction just falls through. I implemented a pass to remove the range check generated before the jump table instruction because it is superfluous. This causes as assertion in MachineBlockPlacement.cpp:

The unchecked assertion that the same register is not added multiple times to the MBB::LiveIn list isn't being respected. Could we add an assertion to check for it? ==== //dwarc/Tools/MetaWare/Toolset/main/dev/llvm/include/llvm/CodeGen/MachineBasicBlock.h#6 - /remote/arctools/marksl/marksl_1/llvm/include/llvm/CodeGen/MachineBasicBlock.h ==== 295,298d294 < /// addLiveIn - Add the

Hello, The function ARMBaseInstrInfo::AnalyzeBranch contains the following piece of code: } else if (I->isReturn()) { // Returns can't be analyzed, but we should run cleanup. CantAnalyze = !isPredicated(I); } else { This could lead to cases where for a block that ends with a conditional return, AnalyzeBranch returns false (i.e. analyzed), both TBB and FBB are

Hi all, I've been investigating a machine verifier failure on the attached testcase, and I'm tempted to say the verifier is wrong and should accept it. Skip the description for the proposed change. On AArch64, the verifier complains with: *** Bad machine code: MBB exits via unconditional branch but doesn't have exactly one CFG successor! *** - function: t4 - basic

Is LiveVariables updated correctly when TII->RemoveBranch and TII->InsertBranch are called in the following piece of code? - MachineBasicBlock::updateTerminator() line 307 of MachineBasicBlock.cpp: if (FBB) { // The block has a non-fallthrough conditional branch. If one of its // successors is its layout successor, rewrite it to a fallthrough // conditional branch.

On Tue, Jan 10, 2017 at 2:31 AM, Peter A Jonsson <pj at sics.se> wrote: > Hi Kyle, > > my apologies for mailing you directly but it seems new user creation is > disabled on the llvm bugzilla. > > We sometime lose edges during IfConversion of diamonds and it’s not > obvious how to reproduce on an upstream target. The documentation for > HasFallThrough says *may*

I am using Ubuntu 10.04 LTS and the wine1.3 ppa (https://launchpad.net/~ubuntu-wine/+archive/ppa). I upgraded this morning using the normal update manager, and I went to run Photoshop CS5 which has been working flawlessly for months, it broke. According to /var/log/apt/term.log I updated from wine1.3.26 to wine1.3.28. I get this error: Code: wine: Call from 0x7b83b332 to unimplemented function

That's true, TBB is limited in compatibility. I don't necessarily think that's where a parallel FLAC API should head, but they're something to be said for Intel's increasing openness with the project and the pipeline design itself. The pipeline could possible be ported to pthreads. Our project was conceived as a way to learn TBB by doing, so we didn't put any time/thought

Hello Anton. Thanks for the comment. > Precisely this is the situation! There're two consecutive branches (br1cond >> and br2uncond). Inside of AnalyzeBranch, there's an opcode swap of br2uncond >> (ex. j_foward to j_backward). There I do BuildMI (newOpcode) and followed by >> br2uncond->eraseFromParent(). This results in br1cond loosing it's >>

On 01/06/2013 07:20 PM, Dmitri Gribenko wrote: > On Mon, Jan 7, 2013 at 12:23 AM, Edward Diener > <eldlistmailingz at tropicsoft.com> wrote: >> On Mageia 2 I have installed the binary clang package clang3.0-7. When I >> tried to build the latest llvm/clang from source using this binary clang >> I get this error: >> >> 1) In file included from >>

Along the same line as Frederick, myself and another university student were able to implement a multi threaded FLAC encoder, but using Intel's Threading Building Blocks (TBB) package. We saw similar near-linear speedup. Our solution is a bit more convoluted since we were learning the API, TBB and writing the encoder all in one 6 week period. We used a pipeline model on the input stream, and

> Precisely this is the situation! There're two consecutive branches (br1cond > and br2uncond). Inside of AnalyzeBranch, there's an opcode swap of br2uncond > (ex. j_foward to j_backward). There I do BuildMI (newOpcode) and followed by > br2uncond->eraseFromParent(). This results in br1cond loosing it's > label/offset. How could I resolve this? Your code is broken.

>> br2uncond->eraseFromParent(). This results in br1cond loosing it's >> label/offset. How could I resolve this? > Your code is broken. AnalyzeBranch should not modify anything. > > I was taking a clue from Mips/MipsInstrInfo.cpp: AnalyzeBranch :( > Could you please suggest appropriate alternative place for such a > modification? Ah sorry, my memory served me

On Feb 8, 2010, at 12:37 AM, Nathan Keynes wrote: > Firstly, the BNE/BA pair should be reduced to a BE (I assume this is > the responsibility of AnalyzeBranch and friends that you mention). Right. Implementing AnalyzeBranch will allow a bunch of block layout and branch optimizations to happen. > However I still wouldn't have expected that to result in the label > being

On Oct 18, 2011, at 5:22 PM, Chandler Carruth wrote: >> As for why it should be an IR pass, mostly because once the selection dag runs through the code, we can never recover all of the freedom we have at the IR level. To start with, splicing MBBs around requires known about the terminators (which we only some of the time do), and it requires re-writing them a touch to account for the

Hello, I am building the SPEC 2006 Benchmark with Clang as the compiler. I have written a function pass in LLVM and I am trying to run that for SPEC by invoking the pass in the build options of SPEC. The build options of SPEC are in a *.cfg config file, which allows us to specify the choice of compiler while building SPEC. (https://www.spec.org/cpu2006/Docs/install-guide-unix.html) The pass

Hello all, we currently do have a problem with samba 3.3.4 on AIX 5.3. We have set up the samba system to integrate in our AD Domain. Integration was successfull (net ads join), wbinfo executes with parameters -ugt without any problems. Our smb.conf content follows at the end of this mail. We have defined just one share as follows: [smbtest] writeable = yes path = /gpfs/fbb/ls/cip valid users

  Hi Aries. Thanks very much! Precisely this is the situation! There're two consecutive branches (br1cond and br2uncond). Inside of AnalyzeBranch, there's an opcode swap of br2uncond (ex. j_foward to j_backward). There I do BuildMI (newOpcode) and followed by br2uncond->eraseFromParent(). This results in br1cond loosing it's label/offset. How could I resolve this? Best regards,