similar to: Question about 'isUnsignedDIType' function on DwarfUnit.cpp

+llvm-dev which got lost somehow > -----Original Message----- > From: Robinson, Paul > Sent: Thursday, March 31, 2016 10:33 PM > To: 'jingu kang' > Subject: RE: [llvm-dev] Question about 'isUnsignedDIType' function on > DwarfUnit.cpp > > > > > -----Original Message----- > > From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On

Hi all, I am currently working on a static analysis aimed at integer arithmetic overflow/underflow detection. We are attempting to build a sound abstract domain (based on Cousot & Cousot-style abstract interpretation), but practically speaking this really requires the ability to figure out the word size and signedness of values in the intermediate representation. I'm well aware

On Tue, Jun 24, 2014 at 2:38 PM, Adrian Prantl <aprantl at apple.com> wrote: > I will take this. > > !5 = metadata !{metadata !"./test.h", metadata !"/Volumes/Data/radar/17052973"} > !6 = metadata !{i32 786489, metadata !5, null, metadata !"test", i32 1} ; [ DW_TAG_namespace ] [test] [line 1] > !4 = metadata !{i32 786434, metadata !5, metadata !6,

+Adrian & Manman, Looks like this is a case of non-DIRef references ending up in the IR, and thus the references not being deduplicated. This could lead to some of the IR bloat that you guys implemented the DIRef stuff to reduce/avoid. The specific issue is that the type is slightly different in the two TUs (since the namespace scope it's contained within is different in the two TUs -

Nah, doesn't look like it. Removed it (& the place I copied it from) in: r324738 Thanks! On Fri, Feb 9, 2018 at 7:28 AM George Rimar <grimar at accesssoftek.com> wrote: > >Totally fair call, sorry it took me a while to come back around to this - > added in r324702 > > Thanks ! Have a question: does it need "requres shell" ? > I tried without and it

Ah, sorry, thanks - removed the "./" prefix entirely. Hope that works - if you happen to test it & find it doesn't, please let me know :) On Fri, Feb 9, 2018 at 7:38 AM George Rimar <grimar at accesssoftek.com> wrote: > I expect r324738 will break on windows, > > as I mentioned I had to change > > > CHECK: ./test.cpp:2:51 > > to > > CHECK:

I expect r324738 will break on windows, as I mentioned I had to change CHECK: ./test.cpp:2:51 to CHECK: {\\|/}}test.cpp:2:51 ? Best regards, George | Developer | Access Softek, Inc ________________________________ От: David Blaikie <dblaikie at gmail.com> Отправлено: 9 февраля 2018 г. 18:35 Кому: George Rimar Копия: Robinson, Paul; llvm-dev at lists.llvm.org; Rafael Avila de Espindola

>Totally fair call, sorry it took me a while to come back around to this - added in r324702 Thanks ! Have a question: does it need "requres shell" ? I tried without and it worked for me under windows (had to change check to CHECK: .{{\\|/}}test.cpp:2:51 though). And I see nothing special probably that might require shell I think. We use cd/rm/cp in LLD testcases without requiring

Please open a bugzilla ticket and attach your testcase. It will allow us to debug and fix the problem. Thanks - Elena From: JinGu [mailto:jingu at codeplay.com] Sent: Saturday, September 16, 2017 00:38 To: Demikhovsky, Elena <elena.demikhovsky at intel.com>; daniel_l_sanders at apple.com <daniel_l_sanders at apple.com>; Jon Chesterfield <jonathanchesterfield at

Totally fair call, sorry it took me a while to come back around to this - added in r324702 On Thu, Nov 16, 2017 at 3:47 PM Rafael Avila de Espindola < rafael.espindola at gmail.com> wrote: > David Blaikie via llvm-dev <llvm-dev at lists.llvm.org> writes: > > > On Thu, Nov 16, 2017 at 11:44 AM Robinson, Paul <paul.robinson at sony.com> > > wrote: > > >

Hi JinGu, We currently have the ResourceCycles list to indicate the number of cpu cycles during which a resource is reserved. We could simply add a ResourceDelay with similar grammar. The MachineScheduler could be taught to keep track of the first and last time that a resource is reserved. Note that the MachineScheduler will work with the instruction itineraries if you choose to implement them.

> extends the elements to 8bit and stores them on stack. Store is responsible for zero-extend. This is the policy... - Elena -----Original Message----- From: jingu at codeplay.com [mailto:jingu at codeplay.com] Sent: Friday, September 15, 2017 17:45 To: llvm-dev at lists.llvm.org; Demikhovsky, Elena <elena.demikhovsky at intel.com>; daniel_l_sanders at apple.com Subject: Re: Question

?Hi ! I have a question about code used for collecting ranges. I was trying to fix PR35199. Its issue that it calls unreachable when calls DWARFObject::getFileName(). We do not implement this method in LLD and it fails. Issue appears when we start to provide .debug_str section to DWARF parser. And it is relative to following code (lines 335-339):

Hi all, I have a compilation failure with 'insert' member function of SmallPtrSetImpl class because the return value is changed from r222334. But the comment of the function is same with before as follows: /// insert - This returns true if the pointer was new to the set, false if it /// was already in the set. std::pair<iterator, bool> insert(PtrType Ptr) { auto p

> so I think we need to use non-extending load for element size less than 8bit on "DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT" like this roughly. > if (N->getOperand(0).getValueType().getVectorElementType().getSizeInBits() < 8) { > return DAG.getLoad(N->getValueType(0), dl, Store, StackPtr, MachinePointerInfo()); > } else { > return

Hi Matthias, >Jingu: Why do you even want a configuration that has LLVM_ENABLE_DUMP but does not have asserts enabled at the same time? My colleague and I am doing custom project using clang/llvm. We have always wanted to use the IR Value's dump() to check our implementation correctly with Debug, Release and another builds. We thought the LLVM_ENABLE_DUMP is for it. If Chris fixes

David Blaikie via llvm-dev <llvm-dev at lists.llvm.org> writes: > On Thu, Nov 16, 2017 at 11:44 AM Robinson, Paul <paul.robinson at sony.com> > wrote: > >> There's no requirement that DW_AT_ranges (or high/low_pc) appear on the >> skeleton CU rather than the DWO CU. So it's quite possible that to get the >> address ranges covered by the CU one would

>Resources and latency are not tied. An instruction is mapped to a scheduling class. A scheduling class is mapped to a set of resources and a per-operand list of latencies. Thanks for your kind explanation. Our heuristic algorithm have needed the latency and the resource per operand to check resource conflicts per cycle. In order to support this with LLVM, I expected a per-operand list of

Hi all, I have faced a little bit of a strange transformation from the TailDuplicatePass In CodeGen. When the pass clones the contents of TailBB into PredBB, the bundled instructions in TailBB are not bundled in PredBB. I think the reason why it is not bundled is that the 'DuplicateInstruction' function does not set up the flag of the first instruction of the bundle in PredBB when it

Hi All, I have faced decoding conflict of DisassemblerTables from TableGen. I have instructions with same encoding and different mnemonic among different architecture versions. I have used Predicates and AssemblerPredicates to distinguish them on Codegen and Assembler but it does not work on Disassembler. When I look at TableGen/FixedLenDecoderEmitter.cpp, once there is decoding conflict,