Displaying 20 results from an estimated 1000 matches similar to: "How to split immediate in assembly output?"
2014 Jul 02
2
[LLVMdev] Passing specific register for an Instruction in target description files.
On Mon, Jun 30, 2014 at 02:40:43AM -0700, Quentin Colombet wrote:
> Hi Arsen,
>
>
> > On Jun 19, 2014, at 10:43 PM, Arsen Hakobyan <artinetstudio at gmail.com> wrote:
> >
> > Hi all,
> >
> > I want to generate an assembly instruction for my target using target
> > description representation of the instruction. The problem is that I want to
2004 Aug 04
5
Asterisk QOS working perfect using sveasoft 3.11g
As seen on my post at:
http://www.sveasoft.com/modules/phpBB2/viewtopic.php?p=28112#28112
This works very well... It does NOT work with stable 4.0! sveasoft
will be issuing a bug fix for this (4.1) in the near future.
Final Rev of working script w/ asterisk support
I'm not going to run alchemy on production machines until it is stablish.
Remember to set your uplink properly and to set
2005 Jun 30
0
Relationship between dyn.load and library.dynam
I am a little confused about the relationship between library.dynam and
dyn.load
>From the documentation:
library.dynam(chname,
Load the specified file of compiled code if it has not been loaded
already, or unloads it. Where chname is a character string naming a
shared library to load.
and
dyn.load(x, local = TRUE, now = TRUE)
Load or unload shared libraries, and test whether a C function
2011 Sep 13
1
using vif from package "car" - "aliased coefficients in the model"
Hello!
I have run a simple regression - lm and created a regression object "myreg".
I can see all the coefficients when I print(myreg).
Then I tried to run vif(myreg) from the package "car".
However, it's giving me an error: in vif.lm(regr.f) : there are
aliased coefficients in the model
Very sorry for my question: Is there any way to get the vif's for all
predictors?
2024 Sep 21
3
store list objects in data.table
I am trying to store regression objects in a data.table
df <- data.frame(x = rnorm(20))
df[, "y"] <- with(df, x + 0.1 * x^2 + 0.2 * rnorm(20))
mydt <- data.table(mypower = c(1, 2), myreg = list(lm(y ~ x, data = df),
lm(y ~ x + I(x^2), data = df)))
mydt
#?? mypower??? myreg
#???? <num>?? <list>
#1:?????? 1 <lm[12]>
#2:?????? 2 <lm[12]>
But mydt[1, 2]
2007 Oct 01
4
data structure with coefficients, and call from lm()
Widows XP
R 2.3.1
I have been trying to make a data structure that will contain both the coefficients from a linear regression along with column and row titles AND the call, i.e.
myreg<-lm(y~x+y+z)
whatIwant<-cbind(c(summary(myreg)$call,"",""),summary(myreg)$coefficients)
Neither the statement above, nor any one of twenty variations I have tried work. I would appreciate
2024 Sep 22
1
store list objects in data.table
Well, you may have good reasons to do things this way -- and you
certainly do not have to explain them here.
But you might wish to consider using R's poly() function and a basic
nested list structure to do something quite similar that seems much
simpler to me, anyway:
x <- rnorm(20)
df <- data.frame(x = x, y = x + .1*x^2 + rnorm(20, sd = .2))
result <-
with(df,
2016 Dec 03
2
Immediate operand for vector instructions
Hello.
I have problems specifying vector instructions with immediate values in TableGen.
I wrote the following specification (I got inspired from the MSA vector instructions
for the Mips back end):
class MSA_I16_FMT<bits<9> opcode>: MSAInst {
bits<16> s16;
let Inst{31-23} = opcode;
let Inst{26-11} = s16;
}
2024 Sep 22
2
store list objects in data.table
Thanks everyone for their responses.
My data is organized in a data.table.? My goal is to perform analyses
according to some groups.? The results of analysis are objects.? If
these objects could be stored as elements of a data.table, this would
help downstream summarizing of results.
Let me try another example.
carsdt <- setDT(copy(mtcars))
carsdt[, unique(cyl) |> length()]
#[1] 3
2009 Jan 29
2
[LLVMdev] undefs in phis
Ok, I understand a bit more of what's going on in my phi example.
Coming into DAGtoDAG we have this code:
bb74:
x = phi(1.0:bb134, %r1450:bb108)
y = phi(undef:bb134, x:bb108)
[...]
bb108:
%r1450 = <expr>
After DAGtoDAG we have:
bb134:
%reg1459 = IMPLICIT_DEF
%reg1458 = 1.0
bb74:
%reg1176 = phi(%reg1458:bb134, %reg1253:bb108)
%reg1177 = phi(%reg1459:bb134,
2015 Feb 27
2
[LLVMdev] LLVM register number for MIPS DAGToDAG
Is it possible to get a register number to which the value is allocated to
in MIPS in DAGToDAG class?
More Specifically:
SDValue Reg3 = Node->getOperand(3);
if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Reg3))
{
op3 = cast<RegisterSDNode>(Reg3)->getReg();
2015 Feb 27
0
[LLVMdev] LLVM register number for MIPS DAGToDAG
> On Feb 27, 2015, at 1:59 AM, Ambuj Agrawal <ambujbwt at gmail.com> wrote:
>
> Is it possible to get a register number to which the value is allocated to in MIPS in DAGToDAG class?
>
> More Specifically:
> SDValue Reg3 = Node->getOperand(3);
> if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Reg3))
>
2016 Mar 22
0
Immediate operand for load instruction, in back end
Hi Alex,
So far, the code you've mentioned only defines a couple tablegen classes but doesn't define the instruction itself. To define the instruction you will also need a 'def' statement. For MIPS MSA, this statement looks like this:
def LD_D: LD_D_ENC, LD_D_DESC;
This defines an instruction (LD_D) with the encoding specified by the LD_D_ENC class, and the operation
2008 Dec 01
0
[LLVMdev] TargetISelLowering
On Dec 1, 2008, at 8:53 AM, Matthijs Kooijman wrote:
> Hi All,
>
> when looking through all the existing targets, I see that each of
> them defines
> <Target>ISelLowering.{cpp,h} files. However, they define a class
> called
> "<Target>TargetLowering" (though the comments in [at least some of]
> those
> files stay the define
2007 Apr 03
2
[LLVMdev] Live intervals and aliasing registers problem
On Mar 27, 2007, at 3:25 PM, Evan Cheng wrote:
>
> On Mar 25, 2007, at 7:12 AM, Christopher Lamb wrote:
>
>> While beginning to add vector registers to a back end I came
>> across the following problem: as soon as I define two sets of
>> registers that have a many-to-one mapping the live interval pass
>> appears to double-kill the mapped-onto register. I
2015 Feb 28
2
[LLVMdev] LLVM register number for MIPS DAGToDAG
Thanks for your reply Quentin. I do understand that the registers are
allocated much later in the pipeline.
I am assuming that the physical registers are allocated before
MipsAsmPrinter class.
I am doing something like
if (MI->getOpcode() == Mips::OPCODE) {
unsigned n = MI->getNumOperands();
for(unsigned i=0 ; i < n ; i++) {
const MachineOperand &MO =
2016 Mar 18
2
Immediate operand for load instruction, in back end
Hello,
I'm trying to define in my new back end, in MyBackendInstrInfo.td file, a vector load
instruction that takes an immediate address operand. (I got inspired from Mips' MSA SIMD
extensions.)
Could you please tell me what's the right way to do it?
Here, the load class has $addrsrc which is a relative address with base a certain
register and offset:
class
2019 Aug 26
1
LLVM X86 backend combineIncDecVector's transform
I think DAGToDAG is too late because the build_vector has already been turned into a constant pool load by then so it’s a little difficult to get back. Maybe we can delay it to !DCI.isBeforeLegalizeOps()? That would at least let the first DAG combine and the post type legalization DAG combine see the add, 1.
+Sanjay as well
From: Amaury Séchet <deadalnix at gmail.com>
Sent: Monday, August
2006 Jan 18
5
Bootstrapping help
Hello,
I am new to using R and I am having problems get boot() to work properly. Here is what I am trying to do:
I have statistic called "cs". cs takes a data matrix (154 x 5) and calculates 12 different scores for me. cs outputs the data as a vector (12 x 1). cs doesn't really use weights, per se, however I have included this as one of the 2 arguments cs can take.
I try
2019 Aug 26
2
LLVM X86 backend combineIncDecVector's transform
No objections from me to make it run later. I didn't see the potential
conflicts when I added that code. Delayed combine, custom lowering, or
DAGToDAGISel all seem like viable options to me.
On Mon, Aug 26, 2019 at 2:04 PM Roman Lebedev <lebedev.ri at gmail.com> wrote:
> I have previously posted these two patches:
>
> [X86][CodeGen][NFC] Delay `combineIncDecVector()` from