similar to: [LLVMdev] Let expressions at file scope combined with defm

Hi Krzystof, regarding your first solution (creating separate instruction), is it possible to somehow have cascading defm? for example, let's suppose aaa is a 3-bit condition a, and bb is a 2-bit condition b, all in one instruction, instead of having one multiclass with 2^5 conditions, is it possible to write 2^3 "a" conditions, and 2^2 "b" conditions, and the rest taken

Hi list, I'm toying with the idea of writing a m680x0 backend for LLVM, and the address modes of this chip are bewildering, to say the least. Here's a rough list off wikipedia for reference: * Register direct o data register, e.g. "D0" o address register, e.g. "A6" * Register indirect o Simple address, e.g. (A0) o

Hi, I'd like to disallow ARM's register-register preload instruction for NaCl (and keep the register-immediate), and instead of my localmod being to delete the 'rs' def from multiclass APreLoad I'd like to do the cleaner thing and have rs require IsNotNaCl. This unfortunately doesn't seem to work because the subsequent defm have their own Requires. The way preloads are

I have been reading the “RFC/bikeshedding: Separation of instruction and pattern definitions in LLVM backends” topic with considerable interest. This is an approach I have been considering for taming our own large instruction set, and it looks like it structures our descriptions better than the conventional approach we have used so far. However, I have another form of TableGen taming that I

On 08/22/2017 03:59 AM, Alex Bradbury via llvm-dev wrote: > On 21 August 2017 at 13:23, Martin J. O'Riordan via llvm-dev > <llvm-dev at lists.llvm.org> wrote: >> But there is a downside. >> >> For each of the above I also have variations that are a result of different >> processor and ISA versions, and because of this I have to use >> ‘multiclass/defm’

Hello all, I have two Tablegen questions in the context of an unconventional architecture. The pertinent details: the architecture has multiple register files that are selected via a bit in the instruction. One of the register files is a traditional one. The other is unconventional in that all source and dest registers are both read from and written to by the instructions. So add special0,

Hi all, I am trying to implement an instruction with no operand for example "clr" in TableGen. ----------------------------------------- e.g. *InstrInfo.td:* class TestInst<string opc, string asmstr, dag oops, dag iops, list<dag> pattern> : Instruction { ... } def int_no_operand : Intrinsic<[]>; class ALU<string opc> : TestInst<opc,

Hello I'm a population ecologist and use R for all my stats and modelling. Recently I have been using R to numerically solve integral projection models. This involves constructing several large matrices. The current code by Easterling (Size-specific sensitivity: Applying a new structured population model. Ecology, 2000, 81, 694-708) uses nested loops to construct the matrices. To speed up the

For example something like STARTUP ( http://wiki.osdev.org/Linker_Scripts#STARTUP) is not accepted by the LLVM LLD. :-/ On Wed, Apr 20, 2016 at 9:08 PM, Sky Flyer <skylake007 at gmail.com> wrote: > Yeah I found it, that's nice. Thanks a milion. > Could you please tell me how can I specify my bootstrap (startup code) in > the linking process? > > > On Wed, Apr 20, 2016

On Tuesday 16 June 2009 19:35, David Greene wrote: > So which is more intuitive and less error-prone? > > defm BLENDPS : sse41_avx_fp_binary_vector_osta_vintrinsic_rmi_rrmi<0x0C, > i32i8imm, "blend", "blend", "f32", 4>; > > or > > defm BLENDPS : sse41_avx_fp_binary_vector_osta_vintrinsic_rmi_rrmi<0x0C, >

# Your mailer is set to "none" (default on Windows), # hence we cannot send the bug report directly from R. # Please copy the bug report (after finishing it) to # your favorite email program and send it to # # r-bugs@r-project.org Reproducible Rterm crash. I drew a complicated graph, then resized the graphics window. R reported > Insufficient memory for resize. Killing device

On Jun 16, 2009, at 5:49 PM, David Greene wrote: > On Tuesday 16 June 2009 19:35, David Greene wrote: > >> So which is more intuitive and less error-prone? >> >> defm BLENDPS : >> sse41_avx_fp_binary_vector_osta_vintrinsic_rmi_rrmi<0x0C, >> i32i8imm, "blend", "blend", "f32", 4>; >> >> or

On Monday 15 June 2009 14:35, Chris Lattner wrote: > > I suppose you could argue that additional parameters specifying > > the source and dest types could be passed, but why bother when > > it is already encoded in the mnemonic? That would just be > > adding error-prone redundancy. > > Why not synthesize the opcode string from the information passed down?

search for VAStart. Cheers, Rafael On 20 April 2016 at 14:18, Sky Flyer <skylake007 at gmail.com> wrote: > Hi Rafael, > > Thanks a lot. > For example the start entry for me is 0x11000 by default which I don't know > where it come from! I thought there should be a default thing that sets this > entry address. > > On Wed, Apr 20, 2016 at 8:05 PM, Rafael Espíndola

Hi, That's what the DecoderMethod is for. Similarly ParserMatchClass for the asm parser and PrintMethod for the asm printer: def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; } def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm), (ops (i32 14), (i32 zero_reg))> { let PrintMethod = "printPredicateOperand";

There is no default linker script. Cheers, Rafael On 20 April 2016 at 11:23, Sky Flyer via llvm-dev <llvm-dev at lists.llvm.org> wrote: > for instance, where is the internal default linker script located? How can I > change the default values, for example the star address... > > On Wed, Apr 20, 2016 at 5:17 PM, Sky Flyer <skylake007 at gmail.com> wrote: >> >>

Hi ES, From what I understand instruction parsing is divided into two parts: - Parsing an operand list (XXXAsmParser::ParseInstruction) - Turning the operand list into an actual instruction (XXXAsmParser::MatchAndEmitInstruction) The second part does the validation (e.g. how many operands, what kind, etc) while the first part only does the parsing. That's why I think in the first part

Hi, the function outer can not apply a constant function as in the last line of the following example: > xg <- 1:4 > yg <- 1:4 > fxyg <- outer(xg, yg, function(x,y) x*y) > fconstg <- outer(xg, yg, function(x,y) 1.0) Error in outer(xg, yg, function(x, y) 1) : dims [product 16] do not match the length of object [1] Of course there are simpler ways to construct a constant

>>>>> Gebhardt, Albrecht <Albrecht.Gebhardt at aau.at> >>>>> on Sun, 19 Mar 2017 09:14:56 +0000 writes: > Hi, > the function outer can not apply a constant function as in the last line of the following example: >> xg <- 1:4 >> yg <- 1:4 >> fxyg <- outer(xg, yg, function(x,y) x*y) >> fconstg

On 08/23/2017 11:35 AM, Jakob Stoklund Olesen wrote: > >> On Aug 22, 2017, at 14:15, Hal Finkel via llvm-dev >> <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: >> >> For situations well beyond TableGen's current language capabilities, >> we have a decision to make. We can continue extending TableGen until >> it can