similar to: [LLVMdev] TableGen Style Conventions

Displaying 9 results from an estimated 9 matches similar to: "[LLVMdev] TableGen Style Conventions"

2018 Aug 28
2
(no subject)
Dear Alex, all, I was looking for fcvt.d.{w,l}{,u} in RISCVInstrInfoD and I'm not sure to understand the current definitions: 138 def FCVT_D_W : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.w"> { 139 let rs2 = 0b00000; 140 } 141 142 def FCVT_D_WU : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.wu"> { 143 let rs2 =
2011 Mar 28
1
idct/fdct.c function calls
Hi. I am trying to find calls of idct/fdct.c functions by tracing png2theora.c calls. But found only: analyze.c:oc_dct_cost2() Where and when idct/fdct/mmxidct/mmxfdct.c functions are used? Mentions of "dct" word: ==== pacify at optima-amd64:/usr/src/libtheora-1.2.0alpha1/lib$ grep dct *.c | cut -f1 -d":" | uniq -c ???? 19 analyze.c ???? 28 decode.c ???? 22 encode.c ????? 4
2011 Mar 28
3
DCT in Theora
> I put debug code in a function in C, > but the function oc_enc_fdct8x8() not called. > Why? There is no function oc_enc_fdct8x8. It's a macro, which usually calls a platform-specific version via _enc->opt_vtable.fdct8x8, though on some platforms, it will call a specific version directly (e.g., oc_enc_fdct8x8_x86_64sse2 on x86-64). All of the functions with platform-specific
2007 Mar 13
0
[LLVMdev] Writing a backend basic information
Hello, Ive started writing a backend to a simple 32bit RISC processor core with the goal of undertaking some flexible instruction processor core research on FPGAs and also to use it for teaching computer architecture. I have a requirement to generate instructions like below, where the (17bit) immediate value is (preferably) omitted if it has a zero value. add %15, %14 add %12, %23 - 18 mov
2015 Jan 11
2
[LLVMdev] Backend Tablegen Instruction Definition
All, in working through the RISCV LLVM backend, I’m running into some trouble in defining the instruction formats for the system instruction. The system instructions follow a pre-defined instruction template (type-I), but differ in that they have no input registers (only the target). The system instructions are defined as: rdcycle Rt I’ve defined a stand-alone instruction definition (as
2009 Oct 07
1
Possible inefficiency in encode.c
Hi, I am very new to Theora, having just started working through the code a few weeks ago. I am working on a requantization tool to reduce bit rates, hopefully on the fly, for some video conferencing work. As I was working through the encoding phase I noticed this line in encode.c: for(ti=_enc->dct_token_offs[pli][zzi];ti<ndct_tokens;ti++){ It's around line 804, but I am
2009 Oct 13
3
Proposal for replacing asm code with intrinsics
Hi, I'm new to Theora and would like to propose several performance optimization using advanced instructions in x86 CPUs (SSE2-SSE4.2). There are several source files in \x86 and \x86_vc which developed using inline assembler. However this cause several maintenance problems: 1) Need to sync gcc & msvc versions 2) Only 32bit environment is supported 3) No support for newer than MMX
2016 Nov 26
4
JMAP support in Dovecot
Hi there, I understand there were discussions to try and develop JMAP support for Dovecot. Is this still in the pipeline for Dovecot 2.5? Regards Andrew Sent from my iPhone
2016 Nov 26
0
JMAP support in Dovecot
Hi Marcus Thanks for your helpful reply. Do you know what is going on with JMAP development into Dovecot 2.5? It's difficult to get any sort of information from the roadmap and there are no Dovecot forums. One of the main reasons I'm interested in JMAP is because of Roundcube Next and also the other clients it will power. Sadly, there has been little going on and having emailed Thomas,