similar to: [LLVMdev] llvm backend porting question ,

I'm having trouble with virtual registers/register allocation in my back-end. Basically the FastRegAlloc pass is generating calls to storeToStackSlot and loadFromStackSlot, in which we build new machine instructions, which are then _not_ processed by the reg allocator. I understand that BuildMI is changing the list of MachInst. that the allocator is iterating over, but we need to have a new

Just noticed that when we generate a custom lowering for some atomics that we forgot to transfer the MemOperand to the new instruction that touches memory. -- Mon Ping Index: lib/Target/X86/X86ISelLowering.cpp =================================================================== --- lib/Target/X86/X86ISelLowering.cpp (revision 53702) +++ lib/Target/X86/X86ISelLowering.cpp (working copy) @@

Hello, after some time I'm trying to build my code with the current CVS of LLVM, and have a problem. The mentioned file, around line 184, contains: if (FixedSlot == FixedSpillSlots+NumFixedSpillSlots) { // Nope, just spill it anywhere convenient. FrameIdx = FFI->CreateStackObject(RegInfo->getSpillSize(Reg)/8,

Hello, I am working on a AVR backend and have a version up and running that will convert LLVM IR code to assembly code for my target. I have written a bunch of instructions from the AVR Instruction Set in AVRInstrInfo.td and not much else. In a simple test case I am attempting to compile (if that is the word you are supposed to use for this operation) test.ll: define i8 @foo(i8 %a, i8 %b) {

Hi Wesley, I've done quite a lot of work on register allocation for stack machines. You might want to look at my papers: http://www.dcs.gla.ac.uk/~marks/euroforth.pdf http://www.dcs.gla.ac.uk/~marks/thesis.pdf Good luck, Mark. -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu on behalf of Wesley J. Landaker Sent: Sun 22/02/2009 23:25 To: llvmdev at cs.uiuc.edu Subject:

Hello, I am developing compiler for the 8-bit PicoBlaze processor in LLVM 2.9. The problem at hand is that the stack spilling code in this architecture modifies the machine FLAGS register (i.e. globally visible state). The LLVM core code does not know about this 'feature' and happily inserts spilling code anywhere it wants, thus (potentially) corrupting live FLAGS. Practically, the FLAGS

Hi all: I wrote some IR transform passes that works perfectly fine at IR level and running through opt -verify on the yielded IR results in no error. However when I try to compile the transformed IR into object code using llc Output.ll -filetype=obj , it asserts out with Assertion failed: (unsigned(ObjectIdx+NumFixedObjects) < Objects.size() && "Invalid Object Idx!"), function

Dear guys, what is the best way to implement a swap of floating point registers in X86? For the integer registers, I am using xchg. Is there a similar instruction for floating point? My function to insert swaps is like: void X86RegisterInfo::swapRegs( MachineBasicBlock & mbb, MachineBasicBlock::iterator mi, unsigned r1, unsigned r2, const TargetRegisterClass

In r155270, I removed code from TableGen that emitted XXXRegisterClass into GenRegisterInfo.inc. This value was just a const pointer to XXXRegClass. So all places that used XXXRegisterClass should be changed to &XXXRegisterClass. I already did the conversion for all targets in the tree so this is a notice to out of tree targets. One of the most common place you might find this is setting up

Hi folks, I am interesting in creating an LLVM backend for a very small stack machine. Before I start in on the actual implementation, I'd like to make sure that I'm on the right track. Any comments, suggestions, warnings, tips, etc would be greatly appreciated. Background ---------- There are a number of small as other embedded microprocessors that are often used in FPGAs such as

On my (out-of-tree) target I have 16 128-bit registers. Unaligned load/store are illegal. (must 16-bytes aligned) 8 of those registers are defined as callee-saved and 8 caller-saved. The default stack size is 4 bytes. The target implements dynamic stack realign to make sure the stack will always be aligned correctly when necessary. Yet I am still getting unaligned load/store when running this

----- Original Message ----- > From: "Francois Pichet" <pichet2000 at gmail.com> > To: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu> > Sent: Monday, November 18, 2013 2:26:30 PM > Subject: [LLVMdev] Unaligned load/store for callee-saved 128-bit registers > > > > On my (out-of-tree) target I have 16 128-bit registers. >

>> Can I tell tablegen to have two encodings and switch between them >> using a predicate? After some deliberations, I modified tablegen to generate several versions of the GenCodeEmitter file. My tablegen now accepts a new command line parameter called "emitter-instfld". This specifies the name of the field in Instruction that holds the encoded bytes. In my target's td

----- Original Message ----- > From: "Hal Finkel" <hfinkel at anl.gov> > To: "Francois Pichet" <pichet2000 at gmail.com> > Cc: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu> > Sent: Monday, November 18, 2013 2:45:53 PM > Subject: Re: [LLVMdev] Unaligned load/store for callee-saved 128-bit registers > > ----- Original

BTW I managed to get around this problem by flagging all the 128-bit registers as caller saved only. On my system, vector registers are more likely to be used on leaf functions anyway. On Thu, Nov 21, 2013 at 3:24 PM, Hal Finkel <hfinkel at anl.gov> wrote: > ----- Original Message ----- > > From: "Hal Finkel" <hfinkel at anl.gov> > > To: "Francois

Hi, I am trying to do a backend to a very simple microcontroller. I have some questions. 1) I have instruction which do "r1 <- r1 op r2", from what I have ssen I must declare them like: let isTwoAddress = 1 in def ADD : FopRR< 0b01010, (outs CPURegs:$sX), (ins CPURegs:$isX, CPURegs:$sY), "ADD $sX, $sY"), [(set

On Apr 27, 2008, at 7:37 AM, Cédric Venet wrote: > Hi, > > I am trying to do a backend to a very simple microcontroller. I have > some > questions. Ok. > 1) I have instruction which do "r1 <- r1 op r2", from what I have > ssen I > must declare them like: > > let isTwoAddress = 1 in > def ADD : FopRR< 0b01010, > (outs

----- Original Message ----- > From: "Francois Pichet" <pichet2000 at gmail.com> > To: "Hal Finkel" <hfinkel at anl.gov> > Cc: "Chad Rosier" <mcrosier at codeaurora.org>, "Jakob Stoklund Olesen" <jolesen at apple.com>, "LLVM Developers Mailing > List" <llvmdev at cs.uiuc.edu> > Sent: Thursday, November

Chris Lattner wrote: > On Sat, 13 May 2006, Vladimir Prus wrote: >> in LLVM CVS the afore-mentioned function has 'const TargetRegisterClass*' >> parameter, that is not documented. >> >> Can somebody explain what does it mean? > > Basically, it gives the target more information about the spill. In > particular, it specifies the register class to use

Jim/Tim/Renato, A few days ago (has it been weeks now?) we discussed a codegen problem on armv4t having to do with lo->lo register copies. I'd like to start that discussion again, this time with a patch. A brief summary of the problem for folks who didn't catch the discussion earlier, and those like me who forget what they ate for breakfast: ;] The mov instruction on armv4t