similar to: tablegen generated enums in tablegen

In BPF, an ADD instruction is defined as a 2 register instruction: 0x0f. add dst, src. dst += src In BPFInstrInfo.td this kind of ALU instruction is defined with: def _rr : ALU_RR<BPF_ALU64, Opc, (outs GPR:$dst), (ins GPR:$src2, GPR:$src), "$dst "#OpcodeStr#" $src", [(set

Sure. Attached is the file but here are the functions. The first uses a fixed bit offset. The second has a indexed bit offset. Compiling with llc -O3, LLVM version 3.7.0svn, it compiles the IR from IsBitSetB() using btq %rsi, %rdi. Good. But then it compiles IsBitSetA() with shrq/andq, which is is pretty much what Clang had generated as IR. shrq $25, %rdi andq $1, %rdi LLVM should be able to

I'm tracking down an X86 code generation malfeasance regarding BT (bit test) and I have some questions. This IR *matches* and then *X86TargetLowering::LowerToBT **is called:* %and = and i64 %shl, %val * ; (val & (1 << index)) != 0 ; *bit test with a *register* index This IR *does not match* and so *X86TargetLowering::LowerToBT **is not called:* %and = lshr i64 %val, 25

This is a patch to X86TargetLowering::LowerToBT() which was hashed over on the Developers list with Intel concurring. It checks whether the -Oz (optimize for size) flag is set or whether the containing function's PGO cold attribute is set. If either are true it emits BT for tests of bits 8-31 instead of TEST. Previously, TEST was always used for bits 0-31 and BT was always used for bits

Which BTQ? There are three flavors. BTQ reg/reg BTQ reg/mem BTQ reg/imm I can imagine that the reg/reg and especially the reg/mem versions would be slow. However the shrq/and versions *with the same operands* would be slow as well. There's even a compiler comment about the reg/mem version saying "this is for disassembly only". But I doubt BTQ reg/imm would be microcoded. -- Ite

> On Jan 22, 2015, at 1:22 PM, Fiona Glaser <fglaser at apple.com> wrote: > > According to Agner’s docs, many CPUs have slower BT than TEST; Haswell has only 0.5 inverse throughput as opposed to 0.25, Atom has 1 instead of 0.5, and Silvermont can’t even dual-issue BT (it locks both ALUs). So while BT does seem have a shorter instruction encoding than TEST for TEST reg, imm32 where

What is the difference between these two fragments (taken from two different tblgen record dumps)? dag OutOperandList = (outs GPR:$rd); dag OutOperandList = (outs R2); The first is from the RISCV backend record dump. There will be a substitution at some point for $rd. In the second, I'm specifying R2, no substitution necessary. If I specify GPR64:R2 or i64:R2 in my Instruction def,

I have a dataframe zeespan. One of the columns has the name "customer". The data in the customer column is text. I would like to return a subset of the dataframe with all rows that DON'T begin with either "ibm" or "exxon", or "sears" in the customer column. I tried .... subset(zeespan, customer != c("ibm" | "exxon" |

I've been unable to come up with the TableGen recipe to match a negated operand. My target asm syntax allows the following transform: FNEG r8, r5 MUL r6, r8, r9 to MUL r6, -r5, r9 Is there a Pattern<> syntax that would allow matching *any* opcode (or even some subset), not just MUL, with a FNEG'd operand? I expect I can define a PatFrag: def fneg_su : PatFrag<(ops

Is that even a valid instruction? I thought TEST only took 32-bit immediates. Fiona > On Jan 22, 2015, at 2:48 PM, Chris Sears <chris.sears at gmail.com> wrote: > > The problem is that REX TEST reg,#(1<<37) is 10 bytes vs 5 bytes for REX BT reg,37. > That's a large space penalty to pay for a possible partial update stall. > > So the idea of generating BT for

Yeah, the alternative is to do movabs and then test, which is doable but I’m not sure if it’s worth it (surely BT + risk of flags merging penalty has to be better than two ops, one of which is ~9-10 bytes). Fiona > On Jan 22, 2015, at 2:59 PM, Chris Sears <chris.sears at gmail.com> wrote: > > My bad on that. So that's what the comment meant. > That means BT is pretty much

On Thu Jan 22 2015 at 3:32:53 PM Chris Sears <chris.sears at gmail.com> wrote: > The status quo is: > > a) 40b REX+BT instruction for the 64b case > b) 48b TEST for the 32b case > c) unless it's small TEST > > > You are currently paying a 16b penalty for TEST vs BT in the 32b case. > That may be worth testing the -Os flag. > You'll want -Oz here, Os

llvm-dev, Thanks so much in advance for any help, tips, or advice you may be able to offer me. I'm going to try to avoid the big-picture description of the project I'm working on, and only talk about the parts that I have trouble with / currently need to implement. -- I've been starting by taking the source code from the "llvm-mc" tool, and working that down into a

Hi, Assume I define registers R0...R15 and two register classes RegA and RegB. RegA contains R0 to R7 while RegB contains R0 to R15. Then I check the machine instruction, it seems that in some cases, the %vreg0 belongs to RegB; in other cases %vreg1 belongs to RegA_RegB. Can you tell me how TableGen decides which is which? At first, I guess &verg0 will be assigned by R8 to R15 only so that

Hey Everyone, I downloaded and installed the X-Lite softphone the other day (the lite version) and cannot seem to get it to work well. Don't get me wrong, it registers with my asterisk server and everything seems to work well, except the call quality really is horrible. I thought it may be the place I was trying it at (DSL) so I took it to the office and tried it right next to the asterisk

Hey Everyone, I am using NuFone for 866 inbound service and I am trying to figure out the callerid part of it. Any call into my * system just shows "Toll Free Call" and will not give me the calling party's caller ID info. Is this just something I have to live with using NuFOne, or did I miss some type of config in * that will grab the callerID other than the inbound 866 number...?

Hello R Experts, How can I assign the name of a data frame with the argument of a function? Specifically I am using RODBC to build local dataframes from SAS datasets on a remote server. I would like the local dataframe have the same name as the source SAS dataset, and the function below is what I am developing. However, the "substitute(table)" on the left side of the assignment

Hi Joe, Le 11/05/2012 02:13, Joe Matarazzo a écrit : > I've been unable to come up with the TableGen recipe to match a > negated operand. My target asm syntax allows the following transform: > > FNEG r8, r5 > MUL r6, r8, r9 > > to > > MUL r6, -r5, r9 > > Is there a Pattern<> syntax that would allow matching *any* opcode (or > even some

Hi Chris, If you have everything setup to test, can you generate the LLVM IR with -03 from 3.4.1 and 3.5 to be sure they match. Then we can focus on the backend. Thanks, Mehdi > On Feb 3, 2015, at 1:58 AM, Chris Sears <chris.sears at gmail.com> wrote: > > So between 3.4.1 and 3.5 since it isn't in 3.4.1 and it is in the current XCode. -------------- next part

Hi Everyone, I read through the list on the issues with the ztdummy driver which I need for MeetMe, but I seem to have come across a problem that I cannot seem to find an answer for. I am running Gentoo 2.6.10 on an Intel box. I have read the the wiki entries on the ztdummy and followed the instructions as they relate to the 2.6 kernel. Everything compiled great, but a modprobe ztdummy