Displaying 7 results from an estimated 7 matches similar to: "tablegen exponential behavior"
2018 Dec 05
2
Strange regalloc behaviour: one more available register causes much worse allocation
Preamble
--------
While working on an IR-level optimisation completely unrelated to register
allocation I happened to trigger some really strange register allocator
behaviour causing a large regression in bzip2 in spec2006. I've been trying
to fix that regression before getting the optimisation patch committed, because
I don't want to regress spec2006, but I'm basically fumbling in
2018 Dec 05
3
Strange regalloc behaviour: one more available register causes much worse allocation
enableAdvancedRASplitCost() does the same thing as ConsiderLocalIntervalCost, but as a
subtarget option instead of a command-line option, and as I’ve said it doesn’t help because
it’s a non-local interval causing the eviction chain (RAGreedy::splitCanCauseEvictionChain
only considers the local interval for a single block, and it’s unclear to me how to make it
handle a non-local interval).
John
2011 Nov 24
2
[LLVMdev] x86 backend assembly - mov esp->reg
Hi,
I've noticed an inconsistency with the x86 backend assembly output in how it treats arguments of a function. Here is a simple test to illustrate the inconsistency:
<from test.c>
void test()
{
char ac, bc, cc, dc, fc;
ac = (char)Rand();
bc = (char)Rand();
cc = (char)Rand();
dc = (char)Rand();
fc = PartialRegisterOperationsTestChar(ac, bc, cc, dc);
}
<from
2014 Aug 13
2
[LLVMdev] Pseudo load and store instructions for AArch64
Hello,
I'm trying to add pseudo 64-bit load and store instructions for AArch64, which
should have latencies set to "1" while being otherwise exactly the same as
normal load and store instructions. Various assertions fire (even different
ones for the same binary, maybe something is uninitialized) and I can't
understand what's wrong. Related pieces added by me:
to
2009 May 21
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote:
> Can you explain why you chose the approach of using a new pass?
> I pictured removing LegalizeDAG's type legalization code would
> mostly consist of finding all the places that use TLI.getTypeAction
> and just deleting code for handling its Expand and Promote. Are you
> anticipating something more
2009 May 21
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 5:26 PM, Eli Friedman <eli.friedman at gmail.com> wrote:
> On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote:
>> Can you explain why you chose the approach of using a new pass?
>> I pictured removing LegalizeDAG's type legalization code would
>> mostly consist of finding all the places that use TLI.getTypeAction
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On May 20, 2009, at 1:34 PM, Eli Friedman wrote:
> On Wed, May 20, 2009 at 1:19 PM, Eli Friedman
> <eli.friedman at gmail.com> wrote:
>
>> Per subject, this patch adding an additional pass to handle vector
>>
>> operations; the idea is that this allows removing the code from
>>
>> LegalizeDAG that handles illegal types, which should be a significant