similar to: [GSoC] Supporting Efficiently the Shift-vector Instructions of the Connex Vector Processor

Hello, Anton, I'd like to add a small reply regarding this GSoC project that I would like to mentor and I discussed also with Andrei. A good part of our GSoC project is indeed related to this Connex back end that it's not yet part of the LLVM source repository - an important thing proposed in the project is that we plan to perform efficient realignment for this Connex vector

Hello. I'd like to advertise the LLVM back end I developed in the last 2 years for the research Connex wide SIMD processor, which can have up to 4096 lanes. The Connex SIMD processor is designed to run efficiently BLAS routins, is an easily reconfigurable low-power processor with scratchpad memory, a shift register for inter-lane communication, a hardware sum-reduction tree and

In btrfs if we mount with "compress" we have no way to disable compressing by remounting (mount -o remount /mnt/btrfs), only by unmounting and mounting without "compress". This patch adds "nocompress" mount option which can be used to remount the filesystem without compression: # mount -o remount,nocompress /mnt/btrfs This option is usefull in cases when we have a

Using LLVM 2.9, the following LLVM IR produces invalid x86 32 bit assembly (a misaligned SSE store). ; ModuleID = 'MisalignedStore' define void @MisalignedStore() nounwind readnone { entry: %v = alloca <4 x float>, align 16 store <4 x float> zeroinitializer, <4 x float>* %v, align 16 br label %post-block post-block: %f = alloca float ret void } If I feed

On Thu, Nov 10, 2011 at 6:13 PM, Aaron Dwyer <Aaron.Dwyer at imgtec.com> wrote: > Using LLVM 2.9, the following LLVM IR produces invalid x86 32 bit assembly > (a misaligned SSE store). > ; ModuleID = 'MisalignedStore' > define void @MisalignedStore() nounwind readnone { > entry: >   %v = alloca <4 x float>, align 16 >   store <4 x float>

In the latest btrfs tools from git it''s a typo: ierdnac-hp ~ # btrfs|grep dafault btrfs subvolume get-dafault <path> btrfs subvolume set-dafault <subvolid> <path> ierdnac-hp ~ # Andrei -- Andrei Popa NOC Manager - Nextgen Communications 0760 683 280

My domains dont see any traffic until you try to connect out from within the domain. Tried this several times and it was consistent. I have no firewall either. running each domain on different cpu probably doesn''t help, although Im no network expert. Here is some info. ================ [root@a root]# xm info system : Linux host : a.b.com release

Hello, I have a data.frame > names(popA) [1] "Year" "Series" "Age" "WM" "WF" "HM" "HF" "BM" [9] "BF" "IM" "IF" "AM" "AF" "Yr" how do i loop over a subset of variables in this frame to create a vector of

Hi Alex, We've only recently managed to get the core scalable vector IR type into the codebase (so it will be present in 9.0); that allows you to write IR with scalable vector types, but there's no backend able to generate code for it yet, and as you mention no support for stepvector (or vscale). Arm will start upstreaming those soon. -Graham > On 13 Jul 2019, at 14:32, Alex Susu via

I had a phone conversation yesterday with Graham, Francesco, and Kristof. There is one more reason to go with the native type change: ARM has already written the code with the SV types, and they have patches ready to be reviewed and integrated in LLVM. As I don't want to stand in the way of getting SVE in LLVM as soon as possible, I will also support the integration of the existing patches

Hello. I am writing a back end in which I combined the existing BPF LLVM back end with the Mips MSA vector extensions (from the Mips back end) I have encountered an error when compiling with llc: the instruction selector uses a vector register instead of a scalar register with type i64 . I have the following part of LLVM IR program: vector.body.preheader:

The saga continues. I've been tracking the interface changes and merging them with the refactoring work I'm doing. I got as far as building stage3 of llvm-gcc but the object files from stage2 and stage3 differ: warning: ./cc1-checksum.o differs warning: ./cc1plus-checksum.o differs (Are the above two ok?) The list below is clearly bad. I think it's every object file in the

Hello. I come back to this older thread. Again, because of i64immSExt32 I receive TableGen error "Could not infer all types in, pattern!" (exact details written below). So far I'm not able to generate selection code with TableGen for the ADD_r* instructions, etc: def i64immSExt32 : PatLeaf<(imm), [{return

Hi, I am looking for a solution to boot MY system on any PC. To store most of the system and all of my data I want to use an USB storage (in my case an external USB harddisk (2.0 capable)). Since booting off an USB device is not an universal thing I would prefer to have a boot disk with a minimal system - just enough to load most (all?) of the system from the attached USB device. Is this an

Looking around today, it appears that TargetRegisterClass and MCRegisterClass only includes a single alignment. This is documented as being the minimum legal alignment, but it appears to often be greater than this in practice. For instance, on x86 the alignment of %ymm0 is listed as 32, not 1. Does anyone know why this is? Additionally, where are these alignments actually defined? I

We don't disable VIRTIO_NET_F_GUEST_CSUM if XDP was set. This means we can receive partial csumed packets with metadata kept in the vnet_hdr. This may have several side effects: - It could be overridden by header adjustment, thus is might be not correct after XDP processing. - There's no way to pass such metadata information through XDP_REDIRECT to another driver. - XDP does not

We don't disable VIRTIO_NET_F_GUEST_CSUM if XDP was set. This means we can receive partial csumed packets with metadata kept in the vnet_hdr. This may have several side effects: - It could be overridden by header adjustment, thus is might be not correct after XDP processing. - There's no way to pass such metadata information through XDP_REDIRECT to another driver. - XDP does not

On Nov 6, 2007, at 6:07 PM, Dale Johannesen wrote: > > On Nov 6, 2007, at 5:45 PM, Bill Wendling wrote: >> $ more testcase.c.t03.generic >> Qux () >> { >> static char C.0[11] = {0}; >> char Bar[11]; >> >> Bar = C.0; >> } >> >> Anyway, it turns out that the gimplifier was generating the correct >> alignment, but it was

Hello everyone. I apologise for the sizeable delay in sending this. The BoF was attended by quite a lot of people and there was general agreement that tablegen needs improvement in some shape of form. However there are many divergent ideas as to how to go about this improvement. Of course this is completely natural, tablegen being a versatile tool used by many different people for many different

Hello. I started implementing a back end in LLVM (and I'm writing some hints I consider useful at https://sites.google.com/site/alexsusu/home/backend-llvm ). Unfortunately, I hit quite a few times very cryptic error messages when compiling with TableGen, which required a few good hours of debugging the TableGen program. The most cryptic error message was when compiling with