similar to: Overlapping register groups in old 8-bit MC6809 processor.

Hi I'm doing a port of Clang/LLVM - purely for the educational value - to the MC6809 (and HD6309 as a dub target) processors. I'll also want to eventually provide direct support for the AM9511 floating-point coprocessor as an option. I'm working with bleeding-edge code from the Git mirror. I've made some pretty decent progress; I copied the llvm/lib/Targets/MSP430 Target to

Hi In my MC6809 backend, in llvm/lib/Target/MC6809/InstPrinter/MC6809InstPrinter.cpp, I have the routine void MC6809InstPrinter::printPCRelImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) { const MCOperand &Op = MI->getOperand(OpNo); ZZ if (Op.isImm()) { int64_t Imm = Op.getImm() + 2; <<<======================== O << "$"; if (Imm

Hi all, I´m trying to convert as a data frame (with format "date") this copied excel column of dates (exposed below), I have tried to save them in a txt file tfr<-read.table("tfra.txt") tfr<-data.frame(tfr) I have tried several things, as date, so on, but always error. And it makes Error en as.Date.default(tfr, "%m/%d/%y") : do not know how to convert

Hi, P-values in Durbin-Watson test obtained through the use of functions available in packages "lmtest" and "car" are different. The difference is quite significant. function "dwtest" in "lmtest" is much faster than "burbinwatson" in "car". Actually, you can take a nap while the latter trying to calculated Durbin-Watson test. My question

Hello we did reinstall a server and we also reinstalled samba ( using the old smb.conf ) Now we have a strange behavior. If i start a dos programm that resides on the samba server from the command line we get the message "access denied" ( Zugriff verweigert ). if I start the same program form windos start/run with the entire path, then the app starts. What is even stranger, after I

Hi, I've come across a problem while working on an LLVM backend for a new target architecture. This architecture has two single-ported register files. Each instruction can only read one operand from each register file, but can write to either. I tried implementing it naïvely in TableGen with two definitions per instruction, so I had: def AllRegs : RegisterClass< ... (add interleave

Hello everyone, I am running into an obscure issue with ExpandPostRA. Does anyone recognizes the following: The pass replaces a real copy with a "transfer" instruction: ********** EXPANDING POST-RA PSEUDO INSTRS ********** ********** Function: main real copy: %R15<def> = COPY %R4, %D2<imp-use,kill>, %D7<imp-use,kill>, %D7<imp-def> replaced by:

I've posted this a couple times here, and a few times in the smb news group, but with no luck. Please, someone help! My setup: samba 1.9.18p8 running on a SCO Unix 5.0.4 machine called WORK (my smb.conf file follows at the end) NT 4.0 Server and workstations with a domain called TRIAL. My problem: I had one user (JOE) that could log onto his machine's domain (NT workstation machine

On Jul 8, 2012, at 3:42 PM, Sergei Larin <slarin at codeaurora.org> wrote: > ********** EXPANDING POST-RA PSEUDO INSTRS ********** > ********** Function: main > real copy: %R15<def> = COPY %R4, %D2<imp-use,kill>, %D7<imp-use,kill>, > %D7<imp-def> > replaced by: %R15<def> = TFR %R4, %D7<imp-def> > > The R4 is a subreg of D2 double

Dear list, I have a question about the interaction between R code and Latex language trough the Sweave function in the package "utils". What I'm trying to do is to write a report. Contrary to the examples shown in the Sweave Manual in which table already constructed by R are "exported" on Latex files, what I would like to do is to build a table in which I combine text and

On Fri, 11 May 2012 10:26:41 -0500 <dag at cray.com> wrote: > Hal Finkel <hfinkel at anl.gov> writes: > > >> Actually, we don't have any problem releasing tests. We have done > >> so before when sending patches. The problem is the people we got > >> the tests from. Some are from proprietary test suites, others are > >> from sensitive

I have this test case in my frontend, which is triggering an assert in llvm master branch: fn fnWithAlignedStack() -> i32 { @setAlignStack(1024); return 1234; } It sets alignstack=1024 in the function attributes (see http://llvm.org/docs/LangRef.html#function-attributes). It's tripping an assert: llvm/lib/IR/Attributes.cpp:134: static llvm::Attribute

Hi Quentin, Am 03.11.2014 um 23:30 schrieb Quentin Colombet <qcolombet at apple.com>: >> Continuing at 4309 >> Match failed at index 4310 >> Continuing at 4322 >> Morphed node: 0x7fef2a033610: i32 = MVrr 0x7fef2a033610 [ORD=21] >> >> >> Does the add operation become a MOVE instruction, or is this a chain of rules? > > Yes, your add becomes

Hi everyone, I am puzzled by several instruction defines in MSP430. 1 def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src), "mov.w\t{$src, $dst}", [ ]>; Because it's an empty dag pattern[ ], by what does instuction selector select intruction 'MOV16rr'? 2 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects =

In MyTargetRegisterInfo.td file, I defined separated register classes for general purpose registers and for the SP register: def GR16 : RegisterClass<"CPU74", [i16], 16, (add R0, R1, R2, R3, R4, R5, R6, R7)>; def SSP : RegisterClass<"CPU74", [i16], 16, (add SP)>; The SP can not be used in general purpose arithmetic instructions, therefore I defined the following

Hi everyone, I practice writing target description file with MSP430 reference. I add a multiply-and-add instruction as below: let isTwoAddress=1 in { def MULADD:Pseudo<(out GR16:$dst), (ins GR16:$src1, GR16:$src2, GR16:$src3), "muladd\t{$dst, $src2, $src3}", [(set GR16:$dst, (add GR16:$src1, (mul GR16:$src2,

Hi, 1. This instruction is not selected automatically by the instruction selector. The instruction combine / select stages insert registercopies, and they are expanded later on by the copyRegToReg() function provided by the MSP430InstrInfo to this MOV16rr. 2. ReMaterializable means there is no need to find a way to preserve the value in a register : the instruction can be just be reissued

Hi, while writing my register allocator, I have come across a case which confuses me because the llvm definition cannot be mapped to machine code. For instance I come across (1) and I reduce it to (2). However a copy instruction cannot move from EDX to CX. What mechanics in LLVM will tell me that I cannot make this move during register allocation, or how can I tell from (1) that I cannot execute

Hi Eli, Thanks for your response. Actually, I look a lot at the ARM and THUMB1 backend implementations, and this certainly help. My architecture also have specific instructions for SP-relative accesses in a similar way than the Thumb1. During frame lowering, specific machine instructions are emitted so there’s no issue there. Also during ISelDagToDag I am able to select the right instructions.

Hi Quentin, >> Yes, the dags in view-isel-dags and view-legalize-types-dags are correct (the add operations are here and are their results are used) and the dags are the same. > > And what about view-sched-dags? The DAG looks like I described below (*) > This one should give you what has been selected. So if this is not correct, you have indeed a problem in the selection