Displaying 20 results from an estimated 200 matches similar to: "llvm combines "ADD frameindex, constant" to OR"
2019 Dec 11
4
modification on lnt to recognize new architecture
Hi,
I have a question regarding to lnt. We are working on NEC SX-Aurora Vector Engine and
preparing for upstreaming it on https://reviews.llvm.org/D69103 and following reviews.
We are running llvm-test-suite to check our modifications often. To run this test suite,
we need to specify our architecture to lnt and make program running under lnt to handle
a few special cases. In order to do so,
2019 Apr 04
2
[RFC] NEC SX-Aurora VE backend
Hello,
we’d like to propose the integration of a new backend into LLVM: NEC
SX-Aurora TSUBASA Vector Engine (VE). We hope to get some feedback here
and at EuroLLVM about the path and proper procedure of merging.
The SX-Aurora VE is a Vector CPU on an PCI-E Accelerator card. It has
48GB memory from six HBM2 stacks, accessible with 1.2TB/s bandwidth, 8
cores with vector and scalar units, each.
2018 May 17
2
New 3.12.7 possible split-brain on replica 3
Hi Ravi,
Please fine below the answers to your questions
1) I have never touched the cluster.quorum-type option. Currently it is set as following for this volume:
Option Value
------ -----
cluster.quorum-type none
2) The .shareKey
2018 May 15
2
New 3.12.7 possible split-brain on replica 3
Thank you Ravi for your fast answer. As requested you will find below the "stat" and "getfattr" of one of the files and its parent directory from all three nodes of my cluster.
NODE 1:
File: ?/data/myvolume-private/brick/dir1/dir2/dir3/dir4/dir5/dir6/dir7/dir8/dir9/dir10/OC_DEFAULT_MODULE/filename.shareKey?
Size: 0 Blocks: 38 IO Block: 131072 regular
2018 May 17
0
New 3.12.7 possible split-brain on replica 3
Hi mabi,
Some questions:
-Did you by any chance change the cluster.quorum-type option from the
default values?
-Is filename.shareKey supposed to be any empty file? Looks like the file
was fallocated with the keep-size option but never written to. (On the 2
data bricks, stat output shows Size =0, but non zero Blocks and yet a
'regular empty file').
-Do you have some sort of a
2018 May 23
0
New 3.12.7 possible split-brain on replica 3
Hello,
I just wanted to ask if you had time to look into this bug I am encountering and if there is anything else I can do?
For now in order to get rid of these 3 unsynched files shall I do the same method that was suggested to me in this thread?
Thanks,
Mabi
?
??????? Original Message ???????
On May 17, 2018 11:07 PM, mabi <mabi at protonmail.ch> wrote:
> ??
>
> Hi Ravi,
2018 May 23
1
New 3.12.7 possible split-brain on replica 3
On 05/23/2018 12:47 PM, mabi wrote:
> Hello,
>
> I just wanted to ask if you had time to look into this bug I am encountering and if there is anything else I can do?
>
> For now in order to get rid of these 3 unsynched files shall I do the same method that was suggested to me in this thread?
Sorry Mabi,? I haven't had a chance to dig deeper into this. The
workaround of
2018 May 15
0
New 3.12.7 possible split-brain on replica 3
On 05/15/2018 12:38 PM, mabi wrote:
> Dear all,
>
> I have upgraded my replica 3 GlusterFS cluster (and clients) last Friday from 3.12.7 to 3.12.9 in order to fix this bug but unfortunately I notice that I still have exactly the same problem as initially posted in this thread.
>
> It looks like this bug is not resolved as I just got right now 3 unsynched files on my arbiter node
2018 May 15
2
New 3.12.7 possible split-brain on replica 3
Dear all,
I have upgraded my replica 3 GlusterFS cluster (and clients) last Friday from 3.12.7 to 3.12.9 in order to fix this bug but unfortunately I notice that I still have exactly the same problem as initially posted in this thread.
It looks like this bug is not resolved as I just got right now 3 unsynched files on my arbiter node like I used to do before upgrading. This problem started
2008 Jan 05
2
Multisim 10 under Wine, don't work?
Hello.
I'm trying to install Multisim 10 under Wine, but it fails with an
"Unhandled MSI Error".
Final error messages on the console are:
renan at gothic:~/ewb_temp$ wine setup.exe
fixme:volume:GetVolumePathNameW
(L"I:\\ewb_temp\\support\\Resource_eng.dll", 0x717e28, 38), stub!
fixme:volume:GetVolumePathNameW (L"I:\\ewb_temp\\support\\nipie.exe",
0x718970,
2014 Apr 04
2
[LLVMdev] 32bit pointers on a (pure) 64bit architecture
Hi Hal,
On Fri, Apr 4, 2014 at 1:22 PM, Hal Finkel <hfinkel at anl.gov> wrote:
> [..]
> Agreed; but what does your *ISelLowering::getPointerTy() function look
> like? Did you override the default implementation? I wonder if returning
> MVT::i64 from this function will make things work for you.
>
> -Hal
>
>
I actually missed implementing this one. But, depending
2011 Feb 14
1
[LLVMdev] broken alignment in stack(caused by bug in SelectionDAGBuilder) causes invalid schedules with r125471 and newer
The following problems happens with architectures, where stack alignment is smaller than the biggest preferred alignment for any data type
SP pointer may point anywhere with alignment of stack alignment (4 in our case)
SelectionDAGBuilder however calls CreateStackObject with preferred alignment is given data type(8 in our problemaric case. The ABI alignment for this data type is only 4)
This
2009 Oct 29
4
deriv() to take vector of expressions as 1st arg?
The deriv() function takes an 'expression' as its first argument). I was
wondering if the this function can take an array or a vector of
expressions as its first argument. Aside, I saw how to give a vector
argument to the second argument.
like to have something like:
deriv(c(~x^2+y^3, ~x^5+y^6), c("x","y"))
the documentation for this function talks about being able to
2016 Dec 11
2
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
Hello.
Will, thanks a lot for pointing me to the MaskedGatherSDNode and mgatherv4i32. I have
to say that the definition of the "multiclass avx512_gather" from
lib/Target/X86/X86InstrAVX512.td is difficult to follow and I prefer not to use it.
I currently have some serious problems with TableGen - it gives an assertion failure:
2017 Oct 13
2
[SelectionDAG] Assertion due to MachineMemOperand flags difference.
Hello,
I've hit an assertion in SelectionDAG where we try to merge 2 loads
that have the same operands but their MMO flags differ. One is
dereferenceable and one is not. I'm not sure what the underlying issue
here is:
1) MDSDNode with the same operands should have the same flags set on
their respective MMO. The fact the flags differ when the
opcode,types,operands and address-space are
2016 Dec 12
0
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
Hello.
I wanted to inform that I fixed the bug from the previous email.
The main reason for the bug was that I thought that the SDNode masked_gather is
returning only 1 value, but it returns 2 (hence, I guess, the earlier reported, difficult
to follow, error: "Assertion `New->getNumTypes() == 1").
masked_gather returns 2 values because:
// SDTypeProfile -
2016 Dec 15
2
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
Hello.
I fixed the bug reported in the previous post on this thread
(<<llvm::MemSDNode::MemSDNode(unsigned int, unsigned int, const llvm::DebugLoc&,
llvm::SDVTList, llvm::EVT, llvm::MachineMemOperand*): Assertion `memvt.getStoreSize() <=
MMO->getSize() && "Size mismatch!"' failed.>>)
The problem with this strange error reported comes from
2014 Apr 04
2
[LLVMdev] 32bit pointers on a (pure) 64bit architecture
Hi Hal,
On Fri, Apr 4, 2014 at 12:44 AM, Hal Finkel <hfinkel at anl.gov> wrote:
> ----- Original Message -----
> > From: "Jeroen Dobbelaere" <jeroen.dobbelaere at gmail.com>
> [... ]
>
> I am trying to get llvm working for an architecture that has 64bit
> > registers, but 32bit addresses.
> > Because of that, I want the pointers to also be
2019 May 14
2
How to change CLang struct alignment behaviour?
Hi John,
On Tue, 14 May 2019 at 17:51, Joan Lluch <joan.lluch at icloud.com> wrote:
> This problem is also shared by the MSP430 target, and it’s very easy to reproduce by just compiling the code that I posted before.
That's some good detective work; it definitely explains what you're
seeing. Since MSP430 is affected it would probably be pretty easy to
upstream an alignment-aware
2009 Mar 18
2
[LLVMdev] Selecting FrameIndex
Hi All
I'm having nightmares with FrameIndexes during my backend development :(
I have ComplexPatterns defined for my two addressing modes (RR and
RI). Most of the time, FrameIndex operands appear to be on load/store
nodes, in which case everything works fine as my custom addressing
modes matchers work fine.
Unfortunately, I now have an add node which has a FrameIndex operand
(this results