Displaying 20 results from an estimated 500 matches similar to: "Dealing with information loss for widened integer operations at ISel time"
2018 Dec 14
2
Dealing with information loss for widened integer operations at ISel time
On Thu, 13 Dec 2018 at 21:41, Friedman, Eli <efriedma at codeaurora.org> wrote:
>
> On 12/13/2018 6:25 AM, Alex Bradbury wrote:
> > There's also likely to be cases where you want to calculate the demanded bits
> > in order to determine if e.g. a W-suffixed instruction can be selected for
> > `(somoeop (zexti32 GPR:$rs1), (zexti32 GPR:$rs2))`. This is easy to match
2015 Sep 18
5
multiply-accumulate instruction
I'm trying to define a multiply-accumulate instruction for the LEON processor, a Subtarget of the Sparc target.
The documentation for the processor is as follows:
===
To accelerate DSP algorithms, two multiply&accumulate instructions are implemented: UMAC and SMAC. The UMAC performs an unsigned 16-bit multiply, producing a 32-bit result, and adds the result to a 40-bit accumulator made
2015 Sep 21
2
multiply-accumulate instruction
I've been looking to see if there's a way to get the instruction below (SMAC) emitted from a higher-level construct, but I'm starting to think this is unrealistic.
To do so, I'd have to tie-in two other instructions: Firstly, clearing the ASR18 and Y register somewhere near the start of the method, then copying out the value of these registers somewhere near the end of the method,
2014 Mar 06
2
'parallel' package changes '.Random.seed'
Hi,
I've implemented parallelization in one of my packages using the
'parallel' package -- many thanks for providing it!
In my package I'm importing 'parallel' and so added it to the
DESCRIPTION file's 'Import:' tag and also added a
'importFrom("parallel", ...)' statement in the NAMESPACE file.
Parallelization works nicely, but my package
2003 Mar 20
1
bind blocking rsync
Hi Guys,
Here is the setup.
LVS NAT cluster with director (dir), backup director (bdir), and two
realservers (rs1 and rs2) running apache webserver.
SSH DSA key-based authentication set up between rs1 and rs2 in order to
facilitate automated (via cron) mirorring of htdocs directories. All
works fine untill I decide to host DNS on the same cluster. As soon as I
start BIND on rs1, ssh no longer
2018 Jun 21
2
add new instruction format
Hi
Im trying to add RISC V Store Instruction for an Experiment on my Target.
The thing is, llvm Store Format gets Register and Pointer Type Operand.
beside this, RISC-V Store Instruction takes source Register, Base Register and offset immediate type. So this takes 3 leafs.
In this case, should I make new SelectionDAG Node in this case? or use BuildMI Instruction to add new Register?
P.S.
2015 Nov 23
3
Qs about TwoOperandAliasConstraint and TIED_TO
in llvm-3.6.2.src
1. when I put this around one of my instruction definitions in my target "InstrInfo.td" file,
let TwoOperandAliasConstraint = "$dst = $rs1" in {
}
I do not see any TIED_TO in the generated GenInstrInfo.inc file for the OperandInfo used by the instruction,
the question is what am I doing wrong ?
2. I've noticed that TwoOperandAliasConstraint
2019 Jul 11
6
Glue to connect two nodes in LLVM backend
Hello everyone,
I wanted to attach a node without affecting the present nodes in any way. I
tried to use MVT::Glue for that but I think I'm missing something as I
could not achieve the below state.
LUI LUI
| |
ADDI ----GLUE---- ADDI
|
store
I've few question about this and Glue node in general, I'll be happy to get
some help on
2014 Sep 01
3
[LLVMdev] understanding DAG: node creation
Hi,
I'm not sure. But in your lowered DAG the chain nodes are the first
operands for you custom nodes, however for the other nodes the chain is
the last operand. I seem to remember that during targetlowering the
chain is the first operand and then it seems to switch over after
ISelDAG, this confused me and may have something to do with the issue
that you are seeing. I really don't
2010 Oct 08
3
Efficiency Question - Nested lapply or nested for loop
My data looks like this:
> data
name G_hat_0_0 G_hat_1_0 G_hat_2_0 G_0 G_hat_0_1 G_hat_1_1 G_hat_2_1 G_1
1 rs0 0.488000 0.448625 0.063375 1 0.480875 0.454500 0.064625 1
2 rs1 0.002375 0.955375 0.042250 1 0.000000 0.062875 0.937125 2
3 rs2 0.050375 0.835875 0.113750 1 0.877250 0.115875 0.006875 0
4 rs3 0.000000 0.074750 0.925250 2 0.897750 0.102000
2019 Aug 27
2
TargetRegisterInfo::getCommonSubClass bug, perhaps.
Hi,
ABCRegister.td :
def SGPR32 : RegisterClass<"ABC", [i32], 16, (add
S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11,
S12, S13, S14, S15
)>;
def SFGPR32 : RegisterClass<"ABC", [f32], 16, (add
S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11,
S12, S13, S14, S15
)>;
===== Instruction selection ends:
...
t8: i32 = ADDrr t37, t32
2016 May 26
2
dumb question about tblgen
Dumb question about llvm-tblgen for "XyzGenInstrInfo.inc"
If I have a pattern in my dot-td-file like this
[(set i32:$dst (add i32:$rs1, i32:$rs2))]
The question is where does the token "i32" come from,
I don't see any definitions for i1, i8, i16, i32, ... in
include/llvm/Target/*.td
while I do see definitions for tokens like
2016 May 26
3
dumb question about tblgen
Quentin,
My real problem is that my target has separate address and data registers.
The way I’d like to try getting better reg-alloc than I am now is to bring out the difference as
Early as possible, so I have added p16, p32, p64 to the enum in “MachineValueType.h”
And I have called addRegisterClass(MVT::p32, &XyzAddrRegsRegClass);
And I have an override for virtual
2019 Nov 25
2
Tablegen PAT limitation?
You are welcome.
I changed the pattern, the same old error pop up again, crash in the same place.
Type set is empty for each HW mode:
possible type contradiction in the pattern below (use -print-records with llvm-tblgen to see all expanded records).
vtInt: (vt:{ *:[Other] })
UNREACHABLE executed at /home/nancy/work/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:824!
2019 Feb 04
7
[RFC] Vector Predication
On Mon, 4 Feb 2019 at 22:04, Simon Moll <moll at cs.uni-saarland.de> wrote:
> On 2/4/19 9:18 PM, Robin Kruppe wrote:
>
>
>
> On Mon, 4 Feb 2019 at 18:15, David Greene via llvm-dev <
> llvm-dev at lists.llvm.org> wrote:
>
>> Simon Moll <moll at cs.uni-saarland.de> writes:
>>
>> > You are referring to the sub-vector sizes, if i am
2016 May 26
0
dumb question about tblgen
Hi Peter,
I would recommend looking into the implementation of the matcher if you want to add more builtin types:
utils/TableGen//DAGISelMatcherGen.cpp
That being said, you can define your own types without having to go through that hassle.
E.g., from AArch64
def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; }]> {
let ParserMatchClass =
2016 May 26
0
dumb question about tblgen
I don’t quite follow why you are doing something like this.
What is the advantage of this instead of just attaching the AddrRegs regsister class as the register class for your instruction?
So that you would have an ADD instruction like
%AddrRegOut = ADD %AddrRegIn1, %AddrRegIn2
What kind of problematic regalloc are you trying to avoid with introducing a new backend data type?
Marcello
> On
2010 Oct 08
1
[LLVMdev] register constraints
Hi,
I have worked with GCC prior to using LLVM, and I am a bit startled to find no way to use an earlier operand as is done in GCC.
For example, a sext instruction on my target takes one the operand of a low-part register, and then sign extends into the full register.I find that there is no way to use for example (set RC:$srsc, sext($src, 16)), or in any other way use a sext operator to perform
2016 May 26
2
dumb question about tblgen
The i32 class is defined in include/llvm/CodeGen/ValueTypes.td along with a
class for every type in MachineValueTypes.h
On Wed, May 25, 2016 at 8:12 PM, Marcello Maggioni via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> I don’t quite follow why you are doing something like this.
>
> What is the advantage of this instead of just attaching the AddrRegs
> regsister class as the
2024 Jul 08
2
Can we reset CSI u mode on client disconnect? via
ssh already restores all TTY flags on exit:
https://github.com/openssh/openssh-portable/blob/V_9_8_P1/sshtty.c#L56-L78
It's possible there are some exit cases that are not hitting the
leave_raw_mode(), but if so then they aren't obvious.
On Sun, 7 Jul 2024, Johannes Altmanninger wrote:
> Some terminals support CSI u style encoding of keystrokes, typically via
> the Kitty keyboard