Displaying 20 results from an estimated 2000 matches similar to: "Quick question: How to BuildMI mov64mi32 arbitrary MMB address to memory"
2018 Sep 22
3
Quick question: How to BuildMI mov64mi32 arbitrary MMB address to memory
Dear Mr. Northover,
Thank you for the quick reply. You are correct about the address-mode
operands :) . I guess an important detail left out was that the basic block
(call it A) that wants to calculate the address of the target stationary
trampoline basic block (call it B) will be moved around in memory during
run-time. Our earlier solution, before the feature was implemented to move
around (A)
2018 Mar 22
2
ARM Backend BuildMI operand issues
Hello everyone,
I'm working on a MachineFunctionPass that inserts a list of instructions
into an Module so a later Pass can work on them.
To do so I load a dummy .ll file created from a main stub, create the
needed function stubs (ModulePass), insert Blocks and create
instructions using BuildMI.
I started with branch instructions:
const TargetMachine &TM = MF.getTarget();
2018 Mar 22
0
ARM Backend BuildMI operand issues
On 03/22/2018 09:29 AM, Julius Hiller via llvm-dev wrote:
> Hello everyone,
>
> I'm working on a MachineFunctionPass that inserts a list of instructions into an Module so a later Pass can work on them.
> To do so I load a dummy .ll file created from a main stub, create the needed function stubs (ModulePass), insert Blocks and create instructions using BuildMI.
> I started with
2018 Mar 23
1
ARM Backend BuildMI operand issues
Thank you for your help Tom
you are totally right with the registers but the command you suggest
also doesn't work.
After some research I found the following thread on the mailing list:
http://lists.llvm.org/pipermail/llvm-dev/2017-February/110086.html
With your help and the information about the condition codes I was able
to resolve the error:
BuildMI(BB, BB.end(), DL,
2014 Dec 08
2
[LLVMdev] Virtual register problem in X86 backend
Hi,
I'm having trouble using virtual register in the X86 backend.
I implemented a new intrinsic and I use a custom inserter. The goal of
the intrinsic is to set the content of the stack to zero at the end of
each function.
Here is my code:
MachineBasicBlock *
X86TargetLowering::EmitBURNSTACKWithCustomInserter(
MachineInstr *MI,
MachineBasicBlock
2014 Oct 28
2
[LLVMdev] Problem in X86 backend (again)
Hi,
I'm still having problems implementing my custom inserter in the X86 backend.
I found a solution to my last problem (http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-October/078296.html), by using a virtual register.
The binary works when it's compiled in -O0, but not in -O1,-O2,...
I really can't figure what I'm doing wrong... Any idea?
Here is the code of my custom
2008 Jul 10
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Cool, that worked. New patch attached...
Cheers,
Gary
Evan Cheng wrote:
> Just cast both values to const TargetRegisterClass*.
>
> Evan
>
> On Jul 10, 2008, at 7:36 AM, Gary Benson wrote:
> > Evan Cheng wrote:
> > > How about?
> > >
> > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass :
> > > &PPC:G8RCRegClass;
>
2014 Dec 10
2
[LLVMdev] Virtual register problem in X86 backend
Hi,
Thx for your help...
Here is the IR code:
; ModuleID = 'foo_bar.c'
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
@.str = private unnamed_addr constant [6 x i8] c"MAIN\0A\00", align 1
; Function Attrs: nounwind uwtable
define i32 @main(i32 %argc, i8** %argv) #0 {
entry:
%retval = alloca i32,
2013 Feb 18
1
[LLVMdev] splitting a branch within a pseudo
Some stuff did not get pasted in properly.
static MachineBasicBlock* ExpandCondMov(MachineInstr *MI,
MachineBasicBlock *BB,
DebugLoc dl,
const MipsSubtarget *Subtarget,
const TargetInstrInfo *TII,
bool isFPCmp, unsigned Opc) {
//
2016 Apr 27
2
[Sparc] builtin setjmp / longjmp - need help to get past last problem
Hi,
I'm implementing __builtin_setjmp and __builtin_longjmp for Sparc 32 bit processors (64 bit later, time allowing).
I'm basing the code on the PowerPC version, which itself is based on the X86 version.
This code is very nearly working, and I've had it working for -O0 optimisation (with a slightly different version to that below), so I know it's close.
However, the PowerPC
2018 Jun 24
2
MachineFunction Instructions Pass using Segment Registers
The size suffix thing is a weird quirk in our assembler I should look into
fixing. Instructions in at&t syntax usually have a size suffix that is
often optional
For example:
add %ax, %bx
and
addw %ax, %bx
Are equivalent because the register name indicates the size.
but for an instruction like this
addw $1, (%ax)
There is nothing to infer the size from so an explicit suffix is
2018 Jun 26
2
MachineFunction Instructions Pass using Segment Registers
This shouldn't have parsed.
movq (%gs), %r14
That's trying to use%gs as a base register which isn't valid. GNU assembler
rejects it. And coincidentally llvm-mc started rejecting it on trunk late
last week. That's probably why it printed as %ebp.
I don't know if there is an instruction to read the base of %gs directly.
Maybe rdgsbase, but that's only available on Ivy
2018 Jun 24
2
MachineFunction Instructions Pass using Segment Registers
Dear All,
Currently I am trying to inject custom x86-64 assembly into a
functions entry basic block. More specifically, I am trying to build
assembly in a machine function pass from scratch.
While the dumped machine function instruction info displays that %gs
will be used, when I perform objdump -d on my executable I am see that
%gs is replaced by %ebp? Why is this happening?
I know it probably
2017 Dec 03
2
5.0.1-rc2 has been tagged
Hi, Tom,
Considering the severity of this bug, I would like to go ahead to push
the fix into release_50 branch. The fix has been tested in the trunk and by
various people as well and I will also make sure all BPF tests passed
before the push.
Thanks!
Yonghong
On Fri, Dec 1, 2017 at 10:18 AM, Y Song <ys114321 at gmail.com> wrote:
> Hi, Tom,
>
> I have a BPF backend bug which is
2018 Jun 24
2
MachineFunction Instructions Pass using Segment Registers
More specifically there is no instruction that can add/subtract segment
registers. They can only be updated my the mov segment register
instructions, opcodes 0x8c and 0x8e in x86 assembly.
I suggest you write the text version of the assembly you want to generate
and assemble it with llvm-mc. This will tell you if its even valid. After
that you can use -show-inst to print the names of the
2014 Oct 29
2
[LLVMdev] Problem in X86 backend (again)
>> // Increment loop variable and jmp
>> BuildMI(*MBB_erase, MBB_erase->end(), db, >> TII->get(X86::ADD64ri32),reg).addReg(reg).addImm(8);
>
> It looks like this instruction is defining virtual register "reg" the second time.
Thx for your answer...
Why would it define it again? I just want to use this register and add something to it...
Cheers
2008 Jul 11
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Hi Evan,
Evan Cheng wrote:
> This does not patch cleanly for me (PPCISelLowering.cpp). Can you
> prepare a updated patch?
This should work, though I won't have access to my test box now until
next Thursday so no guarantees :)
Cheers,
Gary
--
http://gbenson.net/
-------------- next part --------------
Index: lib/Target/PowerPC/PPCISelLowering.h
2008 Jul 08
0
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
PPCTargetLowering::EmitInstrWithCustomInserter has a reference
to the current MachineFunction for other purposes. Can you use
MachineFunction::getRegInfo instead?
Dan
On Jul 8, 2008, at 1:56 PM, Gary Benson wrote:
> Would it be acceptable to change MachineInstr::getRegInfo from private
> to public so I can use it from
> PPCTargetLowering::EmitInstrWithCustomInserter?
>
>
2008 Jul 11
0
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Hi Gary,
This does not patch cleanly for me (PPCISelLowering.cpp). Can you
prepare a updated patch?
Thanks,
Evan
On Jul 10, 2008, at 11:45 AM, Gary Benson wrote:
> Cool, that worked. New patch attached...
>
> Cheers,
> Gary
>
> Evan Cheng wrote:
>> Just cast both values to const TargetRegisterClass*.
>>
>> Evan
>>
>> On Jul 10, 2008, at 7:36
2008 Jul 09
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Ah, didn't see that, that's what comes of trying to do something at
5pm :) I attached an updated patch which creates a virtual register
instead of using R0. How does this look?
Cheers,
Gary
Dan Gohman wrote:
> PPCTargetLowering::EmitInstrWithCustomInserter has a reference
> to the current MachineFunction for other purposes. Can you use
> MachineFunction::getRegInfo instead?