similar to: How to avoid multiple registers definitions in customInserter.

Hi, I have a question related to pre-RA scheduling and spill of registers. I'm writing a backend for two operands instructions set, so FPU operations result have implicit destination. For example, the result of FMUL_A_oo is implicitly the register FA_ROUTMUL. I have defined FPUaROUTMULRegisterClass containing only FA_ROUTMUL. During the instruction lowering, in order to avoid frequent spill

Hi, I've instruction scheduling problem that I cannot further investigate by myself... Could someone give me some clues? After Instruction selection, here is part of the generated instruction. NOP MOV_AB_ro @s1, %fab_roff0 %6:fpuaoffsetclass = COPY %fab_roff0; FPUaOffsetClass:%6 MOV_A_oo %6, def %5; FPUaOffsetClass:%6,%5 MOVSUTO_A_iSLo 24575, def %7;

Hi, I'm implementing the built_vector as an IMPLICIT_DEF followed by INSERT_SUBREGs. This approach is the one of the SPARC architecture. def : Pat<(build_vector (f32 fpimm:$a1), (f32 fpimm:$a2)), (INSERT_SUBREG(INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), (i32 (COPY_TO_REGCLASS (MOVSUTO_A_iSLo (bitcast_fpimm_to_i32 f32:$a1)), FPUaOffsetClass)), A_UNIT_PART),

Could anybody quickly explain why PHI nodes instructions are necessary in machine code? And why the code in LiveVariables.cpp which looks at those PHI nodes (line 249 and below) is necessary. The reason I'm asking is that I try to support 64-bit comparison and I do it by generating code like: // if high1 cond high2: goto operand0 // if high1 reverse_cond high2:

On Thu, Jul 08, 2004 at 08:06:29PM +0400, Vladimir Prus wrote: > Could anybody quickly explain why PHI nodes instructions are necessary > in machine code? And why the code in LiveVariables.cpp which looks at > those PHI nodes (line 249 and below) is necessary. LLVM Machine code is in SSA. Let's say you want to do r = a cond b But doing this: if (a cond b) then r = 1

Hi, For the development of a new micro-controller backend, I try to lowering the following store SDNode: t5: ch = store<ST2[%ptr2](align=4)> t0, Constant:i16<3>, FrameIndex:i16<1>, undef:i16 I have defined the following instruction and associated DAG pattern. def MOVSUTO_A_i32o : CLPFPU_A_i32o_Inst<0b1000001101,

PHI nodes within machine code were originally used by the Sparc back-end but they turned out not to be necessary. Instead, LLVM phis are lowered to copy instructions in the machine code (I believe this happens just after instruction selection). As far as I know, the machine PHI nodes are not used by the x86 back-end and you shouldn't need them if you insert the right copies. --Vikram

Misha Brukman wrote: > LLVM Machine code is in SSA. This explains quite a lot. I though it's possible to just reduce convert phis into copy instructions in predecessors -- all of which will have the same destination register. > gets you two definitions of r. So we have machine PHI nodes merge the > two possible values into one for result of r. These phis get removed > after

Hi, In the context of MachineCode custom inserter, I'm trying to enforce the mapping of virtual register to a physical one. According to the documentation https://llvm.org/docs/CodeGenerator.html#mapping-virtual-registers-to-physical-registers There are two ways: the direct one and the indirect ones. The indirect ones refer VirtRegMap class that I've never found. So I tried the direct

Hi again, After further investigation, I've found that the private PhysRegUseDefLists array ("head of use/def list for physical register") from MachineRegisterInfo class seems to be empty. But I didn't found any methods for updating such data structure. How/where this "use/def list" should be managed ? Is the documentation

in llvm-3.6.2.src 1. when I put this around one of my instruction definitions in my target "InstrInfo.td" file, let TwoOperandAliasConstraint = "$dst = $rs1" in { } I do not see any TIED_TO in the generated GenInstrInfo.inc file for the OperandInfo used by the instruction, the question is what am I doing wrong ? 2. I've noticed that TwoOperandAliasConstraint

Hi Dominique, From your description it is not really clear what you are trying to do here. It may be the case that the goal you are trying to accomplish can be better reached using a different approach. In general, optimizations don't try to assign physical registers, that's done by the register allocation passes. There are some cases when target-specific passes use physical

On Mon, Jun 30, 2014 at 02:40:43AM -0700, Quentin Colombet wrote: > Hi Arsen, > > > > On Jun 19, 2014, at 10:43 PM, Arsen Hakobyan <artinetstudio at gmail.com> wrote: > > > > Hi all, > > > > I want to generate an assembly instruction for my target using target > > description representation of the instruction. The problem is that I want to

Hi all, I want to generate an assembly instruction for my target using target description representation of the instruction. The problem is that I want to add direct register to be chose as an output register for my target. Does it possible to do with an instruction definition in TARGETInstrInfo.td file? May be someone could help with an example? Currently I have seen that we can pass the name

Hi Krzysztof, Thanks for your response. I was trying to map function input parameters to machine specific registers. My solution I found is based to the RegInfo.setSimpleHint() API. Here is the body of the parameters loop of TargetLowering::LowerFormalArguments VReg = RegInfo.createVirtualRegister(RC); RegInfo.setSimpleHint(VReg,CLP::FA_ROFF1+i);

Here is a last example to illustrate my concern. The problem is about the lowering of node t13. Initial selection DAG: BB#0 '_start:entry' SelectionDAG has 44 nodes: t11: i16 = Constant<0> t0: ch = EntryToken t3: ch = llvm.clp.set.rspa t0, TargetConstant:i16<392>, Constant:i32<64> t5: ch = llvm.clp.set.rspb t3,

The DAG dumping will try to print some of the nodes "inline" (i.e. where they are used) to make the output more readable, so the dump of the DAG may not strictly reflect the node ordering. -Krzysztof On 5/4/2018 8:18 AM, Dominique Torette via llvm-dev wrote: > Here is a last example to illustrate my concern. > > The problem is about the lowering of node t13. > >

Hi, Is there a kind of scope mechanism in the instruction lowering pattern language in order to control where instructions are inserted or how they are later reordered during the SelectionDiag linearization? I know the glue chain that stick instructions together. But such mechanism in not provided in instruction lowering pattern. I'm facing many situations where some patterns are lowered into

Krzysztof, Thanks for your interest to my questions. In order to clarify the context, here is the C source file of my test case. The 3 builtins initialize some stack pointers. They have to be executed before any other instruction. extern float fdivfaddfmul_a(float a, float b, float c, float d); volatile static float x1,x2,x3,x4; void _start(void) { float res;