similar to: [DWARF] prologue_end fix not working for VLIW

Hi there, I wondered whether anyone could give me any advice about counting assembly instructions when using MCJIT? For performance regression testing I would like to be able to count the number of instructions generated during the jit compilation of a given module. The Statistic class, as far as I understand, cannot collect this data per-module (per-ExecutionEngine/per-MCJIT), and there is

Hi, I noticed that a while ago the isSSA flag was removed from MIR, and this property is now computed. However, the deduction only checks the virtual registers (whether they are assigned to more than once). Now I have MIR tests which live after RA, so they only contain physical registers, so the parser determines they are in SSA form. These tests now fail because some of our passes can be

Can I assume we're talking about MCJIT since a file format and relocations are involved? Some changes are required in order to get MCJIT to generate ELF object files. Eli Bendersky submitted a patch some time ago to modify the target triple code to enable this, but after a bit of discussion there didn't seem to be a consensus for accepting this proposal. If you want to try it out, the

Hi, In X86MachObjectWriter::RecordX86Relocation I found the comment if (Target.isAbsolute()) { // constant // SymbolNum of 0 indicates the absolute section. // // FIXME: Currently, these are never generated (see code below). I cannot // find a case where they are actually emitted. Type = macho::RIT_Vanilla; } Is the FIXME still true? I've got some code that

Hi Jim, Andrew, Thanks, I read the discussions about using ELF + MCJIT + Windows and was hoping MachO would work just as well. Since you don't need to modify LLVM to be able to output MachO this was my first choice. But are you saying MachO will not work as well as ELF? Thanks for the patch Andrew, that will have to be my plan B in this case. Verena On 29/06/2012 23:47, Kaylor, Andrew

Hi Verena, Windows + MachO is likely to run into lots of problems once you start passing in non-trivial code. The relocation model is very tied to Darwin. I believe some folks doing JIT on Windows have had some success w/ ELF. Hopefully someone more familiar with the specifics of that will chime in. -Jim On Jun 29, 2012, at 8:58 AM, Verena Beckham <verena at codeplay.com> wrote: >

Hi, anyone know anything about copy propagation? Matthias, I see this was your code originally? Was there some assumptions you made? I'm hitting an assertion in MachineCopyPropagation::isNopCopy: if (Src == PreviousSrc) { assert(Def == PreviousDef); return true; } This code compares two COPY instruction to see whether they are effectively "the same". The assert assumes

Hi Verena, I think that we can count the number of instructions with "-stats" command line option. As you mentioned, this option uses Statistic class like "STATISTIC(EmittedInsts, "Number of machine instrs printed");" I don't know exactly about parallel code generation environment but this option seems like to work correctly in common case as following. This is

Thu Jul 12 03:42:12 CDT 2012, Verena Beckham verena at codeplay.com : > I would not say it is trivial, having done it myself. > > MCJIT also doesn't support multiple modules, and it does not do JITing > on demand, instead, it does all of it at the same time in the > constructor (unless that is what you call "not lazy"). > So depending on how you've written your

Hi Pawel, Some of the issues I have come across (from memory!) are * MCJIT doesn't work on Windows, because it doesn't support COFF. If you want to use it on Windows you have to either target Mach-O (not clear whether that will work in general) or ELF (need to get a patch from Intel to be able to use this). * Make sure you include MCJIT.h and link in MCJIT.lib, otherwise (even if

Hi, You cannot call removeModule on a JIT with no modules: jitstate will be 0 and therefore we have a null-pointer exception. The function returns a boolean for success/failure, however, so you would expect to be able to call it and get false back. Should we be checking for jitstate != 0 before accessing the variable? - if (jitstate->getModule() == M) { + if (jitstate &&

We are currently doing something similar to your third option in Hexagon backend. But it is a VLIW so predication is not the only reason for that. Sergei --- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation > -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > On Behalf Of Marcello

Hi, I think there might be a bug in the tail duplicator (called from MachineBlockPlacement in my case), when duplicating a block that contains an implicit fall-through. Suppose you have the following blocks BB#1: Predecessors according to CFG: BB#2 ... conditional_branch <BB#3> < implicit fall-through to BB#2 > Successors according to CFG: BB#2 BB#3 BB#2:

Hello, I'm working on a compiler based on LLVM for a SIMD architecture that supports instruction predication. We would like to implement branching on this architecture using predication. As you know the LLVM-IR doesn't support instruction predication, so I'm not exactly sure on what is the best way to implement it. We came up with some ways to do it in LLVM: - Do not add any

Hi, I wondered whether the AggressiveAntiDepBreaker can properly handle predicated instructions. At the end of PrescanInstruction the "DefIndices" array is updated with the destination register without checking whether the instruction is predicated. That shortens the live range: Later on, in HandleLastUse we check whether the register IsLive, which considers only

On Mar 3, 2014, at 8:53 AM, Pierre-Andre Saulais <pierre-andre at codeplay.com> wrote: > Hi Andrew, > > We are currently using a custom model where scheduling information is attached to each MCInstrDesc through tablegen, and we're trying to move to one of LLVM's models. > > To expand on what JinGu mentioned, our target has explicit ports that are used to read and

On Mar 4, 2014, at 10:05 AM, Pete Cooper <peter_cooper at apple.com> wrote: > > On Mar 3, 2014, at 2:21 PM, Andrew Trick <atrick at apple.com> wrote: > >> >> On Mar 3, 2014, at 8:53 AM, Pierre-Andre Saulais <pierre-andre at codeplay.com> wrote: >> >>> Hi Andrew, >>> >>> We are currently using a custom model where

Hi list, I happened to read below thread (written in 3 years ago). I think I may need this ReadAdvance feature to work with my ARCH. It is about the scheduler info which describes reading my ARCH's vector register. There are different latencies since forwarding/bypass appears. I give it as below example: def : WriteRes<WriteVector, [MyArchVALU]> { let Latency = 6; } ... def

Hi All, I have a question about TableGen RegisterClass definition. I need to map different size of MVTs into a register class as below. def TestReg : RegisterClass<"Test", [v8i32, v4i32], ...> When I look at TableGen and CodeGen, it looks the types are used as following: 1. MCRegisterClass's RegSize and Alignment 2. SpillSize in TableGen 3. Type constraint for instruction

On Feb 19, 2014, at 1:54 PM, jingu <jingu at codeplay.com> wrote: > Hi Andy, > > I am trying to schedule and packetize instructions for VLIW at post-RA > stage or final codegen stage, where code transformations are not allowed > any more, because hardware can not resolve resource conflict. There is a > simple example as following: > > ADD dest_reg1, src_reg1,