similar to: Lowering ISD::TRUNCATE

Hi all, I have been looking at the way LLVM optimizes code before forwarding it to the backend I develop for my company and while building define i32 @test_extract_subreg_func(i32 %x, i32 %y) #0 { entry: %conv = zext i32 %x to i64 %conv1 = zext i32 %y to i64 %mul = mul nuw i64 %conv1, %conv %shr = lshr i64 %mul, 32 %xor = xor i64 %shr, %mul %conv2 = trunc i64 %xor to i32

Hello. I write backend for Z80 cpu and I have some trouble with lowering load/store nodes to different machine opcodes. Some target instructions work with specified registers (not all registers in RegisterClass). Often it's one or two registers. I don't understand how use ComplexPattern in this case. But if I don't use ComplexPattern I'll have other problems - not all

Maybe I didn't describe the question very well. I want to match these patterns: (and (mul node:$val0, node:$val1)) (and (add node:$val0, node:$val1)) (and (sub node:$val0, node:$val1)) (and (udiv node:$val0, node:$val1)) into "four" different machines instructions, respectively: MUL_AND ADD_AND SUB_AND UDIV_AND That is, this machine is capable of doing an

I was looking through the InstCombine pass, and I was wondering why signed division is not considered a valid operation to combine in the canEvaluateTruncated function. This means, given the following code: %conv = sext i16 %0 to i32 %conv1 = sext i16 %1 to i32 %div = sdiv i32 %conv, %conv1 %conv2 = trunc i32 %div to i16 * Assume %0 and %1 are registers created from simple 16-bit loads. We

On Mon, Dec 10, 2012 at 2:13 PM, Matthew Curtis <mcurtis at codeaurora.org> wrote: > Hello all, > > I wanted to get some feedback on this patch for ScalarEvolution. > > It addresses a performance problem I am seeing for simple benchmark. > > Starting with this C code: > > 01: signed char foo(void) > 02: { > 03: const int count = 8000; > 04: signed char

Hello all, I wanted to get some feedback on this patch for ScalarEvolution. It addresses a performance problem I am seeing for simple benchmark. Starting with this C code: 01: signed char foo(void) 02: { 03: const int count = 8000; 04: signed char result = 0; 05: int j; 06: 07: for (j = 0; j < count; ++j) { 08: result += (result_t)(3); 09: } 10: 11: return result; 12: } I

Hi, I noticed that when dividing with signed 8-bit values the IR uses a 32-bit signed divide, however, when unsigned 8-bit values are used the IR uses an 8-bit unsigned divide. Why not use a 8-bit signed divide when using 8-bit signed values? Here is the C code and IR: char idiv8(char a, char b) { char c = a / b; return c; } define signext i8 @idiv8(i8 signext %a, i8 signext %b) nounwind

Hi Sanjay, thank you a lot for your answer. I understand that in your examples it is desirable that `foo` and `goo` are canonicalized to the same IR, i.e., something like `@goo`. However, I still have a few open questions, but please correct me in case I'm thinking in the wrong direction. > Am 21.07.2016 um 18:51 schrieb Sanjay Patel <spatel at rotateright.com>: > > I've

The topic of Ra and jit has come up on this list recently (see http://www.milbo.users.sonic.net/ra/index.html) so I thought people might be interested in this little demo. For it I used my machine, a 3-year old laptop with 2Gb memory running Windows XP, and the good old convolution example, the same one as used on the web page, (though the code on the web page has a slight glitch in it). This

I'm working on a Z80 backend and am trying to efficiently lower SEXT, specifically 8 to 16 bit, in LowerOperation() according to the following rules: The Z80 has 8 bit registers and 16 bit registers, which are aliased versions of two 8 bit registers. 8 bit registers are named A, H, L, D, E and some more. 16 bit registers are HL (composed of H + L), DE (D + E) - and some more - with L and

Hi All. I'm writing storeRegToStackSlot and loadFromStackSlot function for my Target. This Target can store/load one byte (not all word) from FrameIndex. If I need to store 16 bit register I will must to split it to two instruction like this: BuildMI(MBB, MI, dl, get(Z80::LD8xmr)) .addFrameIndex(FrameIndex).addImm(0) .addReg(SrcReg, 0, Z80::subreg_lo); BuildMI(MBB, MI, dl,

Thanks so much for your feedback Simon. I am not sure that what I am proposing here is at odds with what you're referring to (here and in the PR you linked). The key difference AFAICT is that the pattern I am referring to is probably more aptly described as "reducing scalarization" than as "vectorization". The reason I say that is that the inputs are vectors and the output

Inspired by Jason Turner's talk at CppCon 2016: Jason Turner “Rich Code for Tiny Computers: A Simple Commodore 64 Game in C++17” I got interested in writing a Zilog Z80 backend for LLVM. Jason actually did no such thing, but instead wrote a x86-to-6502 translator (reassembler he calls it) https://github.com/lefticus/x86-to-6502 So I'm now trying to bootstrap this project. Goal: - be

Hi Dmitriy, As you've seen our current spill code assumes that spill/reloads are single instructions. I think the best way to work around this is to introduce load/store pseudo-instructions and expand these after register allocation. Cheers, Lang. On Sat, Feb 23, 2013 at 12:15 AM, Dmitriy Limonov <earl at excluzive.ws> wrote: > Hi All. > > I'm writing

Hi, I'm trying to revive jacobly0's Z80 back-end (from https://github.com/jacobly0/llvm-z80) and build it with a current version of LLVM. Apart from some interface changes, I'm stuck at building the tables. Specifically, the generation of the DAG instruction selector causes an assertion in the table generator: Assertion failed: Ops.size() >= NumSrcResults &&

Dear list, I have to read a not-so-small bunch of not-so-small Excel files, which seem to have traversed Window 3.1, Windows95 and Windows NT versions of the thing (with maybe a Mac or two thrown in for good measure...). The problem is that 1) I need to read strings, and 2) those strings may have various encodings. In the same sheet of the same file, some cells may be latin1, some

Absolutely. We do it for scalars, so it would likely be a matter of just extending it. But that is one example. The issue of extracting elements, performing an operation on each element individually and then rebuilding the vector is likely more prevalent than that. At least I think that is the case, but I'll do some analysis to see if it is so or not. On Sat, Jan 11, 2020 at 6:15 PM Craig

Hello. I am playing with LLVM and trying to make Z80 (Zilog Z80) backend. The source code is attached. I have succesfully made some simple test. But now I have problem with ADD instruction. The source C code is: typedef struct { unsigned char id1; unsigned char id2; unsigned char id3; } testS; void simple() { testS test; test.id1 = 0x40; test.id2 = 0x80; test.id3 = 0xc0; } It

Dear R helpers Suppose val1 = c(10, 20, 35, 80, 12) val2 = c(3, 8, 11, 7) I want to select either val1 or val2 depending on value of third quantity val3. val3 assumes either of the values "Monthly" or "Yearly". If val3 = "Monthly", then val = val1 and if val3 = "Yearly", then val = val2. I tried the ifelse statement as ifelse(val3 =