Displaying 20 results from an estimated 4000 matches similar to: "MachineFunction Instructions Pass using Segment Registers"
2018 Jun 24
2
MachineFunction Instructions Pass using Segment Registers
More specifically there is no instruction that can add/subtract segment
registers. They can only be updated my the mov segment register
instructions, opcodes 0x8c and 0x8e in x86 assembly.
I suggest you write the text version of the assembly you want to generate
and assemble it with llvm-mc. This will tell you if its even valid. After
that you can use -show-inst to print the names of the
2018 Jun 24
2
MachineFunction Instructions Pass using Segment Registers
The size suffix thing is a weird quirk in our assembler I should look into
fixing. Instructions in at&t syntax usually have a size suffix that is
often optional
For example:
add %ax, %bx
and
addw %ax, %bx
Are equivalent because the register name indicates the size.
but for an instruction like this
addw $1, (%ax)
There is nothing to infer the size from so an explicit suffix is
2018 Jun 26
2
MachineFunction Instructions Pass using Segment Registers
This shouldn't have parsed.
movq (%gs), %r14
That's trying to use%gs as a base register which isn't valid. GNU assembler
rejects it. And coincidentally llvm-mc started rejecting it on trunk late
last week. That's probably why it printed as %ebp.
I don't know if there is an instruction to read the base of %gs directly.
Maybe rdgsbase, but that's only available on Ivy
2018 Sep 22
3
Quick question: How to BuildMI mov64mi32 arbitrary MMB address to memory
Dear Mr. Northover,
Thank you for the quick reply. You are correct about the address-mode
operands :) . I guess an important detail left out was that the basic block
(call it A) that wants to calculate the address of the target stationary
trampoline basic block (call it B) will be moved around in memory during
run-time. Our earlier solution, before the feature was implemented to move
around (A)
2018 Sep 22
2
Quick question: How to BuildMI mov64mi32 arbitrary MMB address to memory
Dear All,
I am working on a x86 backend machineFunction pass, where I am trying to
save the hard coded address of an arbitrary machine basic block to memory
in ASM. I know the assembly needed for this but am lost at how to construct
the BuildMI().
Note that these machine basic blocks are not entry's to a function. but in
the middle of the function. so using addGlobalAddress or
2007 Oct 04
3
[LLVMdev] RFC: Tail call optimization X86
Comments:
CheckDAGForTailCallsAndFixThem -
1.
for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
+ BI = prior(DAG.allnodes_end()); BI != BE; BI--) {
Please use pre-decrement instead of post-decrement.
2. The function is slower than it should be. You are scanning all the
nodes in the DAG twice. You should just examine DAG.getRoot() to make
determine whether it's a
2012 Sep 11
1
[LLVMdev] Need Help Understanding Operands in X86 MachineFunctionPass
-----Original Message-----
From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of John Criswell
Sent: Tuesday, September 11, 2012 1:42 PM
To: Steve Checkoway
Cc: LLVMdev at cs.uiuc.edu
Subject: Re: [LLVMdev] Need Help Understanding Operands in X86 MachineFunctionPass
...
>
>> The code for adding the 32-bit instruction is:
>>
>>
2012 Sep 11
1
[LLVMdev] Need Help Understanding Operands in X86 MachineFunctionPass
On Sep 11, 2012, at 10:57 AM, John Criswell wrote:
> I'm working on an X86 MachineFunctionPass that adds prefetch instructions to a function. I have code that adds a "prefetchnta <constant address>" instruction to x86 32-bit code. What I want to do is to add a "prefetchnta <constant address>" instruction to x86_64 code.
Given that you don't actually
2007 Oct 05
0
[LLVMdev] RFC: Tail call optimization X86
Hi Evan,
I incoporated the changes you request but to the following i have got
a question:
> Also, moving the option
> there will allow us to change fastcc ABI (callee popping arguments)
> only when this option is on. See Chris' email:
I am not to sure on that. because that would make modules compiled
with the flag on incompatible with ones compiled without the flag off
as
2012 Sep 11
0
[LLVMdev] Need Help Understanding Operands in X86 MachineFunctionPass
On 9/11/12 12:10 PM, Stephen Checkoway wrote:
> On Sep 11, 2012, at 10:57 AM, John Criswell wrote:
>
>> I'm working on an X86 MachineFunctionPass that adds prefetch instructions to a function. I have code that adds a "prefetchnta <constant address>" instruction to x86 32-bit code. What I want to do is to add a "prefetchnta <constant address>"
2016 Apr 15
3
[Sparc] Load address with SETHI
Hi,
I'm trying to implement __builtin_setjmp / __builtin_longjmp for Sparc processors. I think I'm very close, but I can't work out how to issue BuildMI-type instructions to load the address of the recovery location (set in setjmp) into a register using the SETHI / OR combination. I can't see any equivalent code anywhere else in Sparc.
I imagine this is similar if I try to make a
2015 Feb 11
2
[LLVMdev] deleting or replacing a MachineInst
There are 11 BuildMI() functions in MachineInstrBuilder.h including four
using the iterator and one using an instruction. But I just don't think
that's it. The creation of the new instruction works fine (works fine with
OldMI as well) and the new instruction is present in the assembly output.
The problem is removing the old instruction correctly.
> The loop header needs to be
2013 Feb 15
2
[LLVMdev] build a machine instruction by itself
On 02/15/2013 03:07 PM, Jakob Stoklund Olesen wrote:
> On Feb 15, 2013, at 1:21 PM, Reed Kotler <rkotler at mips.com> wrote:
>
>> I want to have some functions that create machine instructions, not specifying which machine function or basic block or iterator they are part of.
> All machine instructions must be created by a machine function. It provides the context for memory
2013 Feb 16
0
[LLVMdev] build a machine instruction by itself
I ended up settling on a scheme which I'm not completely happy with but
it's the best I can see to do.
const MCInstrDesc& AddiuSpImm(int64_t Imm) const;
and then
if (isInt<16>(-Remainder))
BuildMI(MBB, I, DL, AddiuSpImm(-Remainder)).addImm(-Remainder);
So the AddiuSpImm choses which instruction description to use depending
on the immediate value and then
2015 Feb 11
2
[LLVMdev] deleting or replacing a MachineInst
This seems a very natural approach but I probably am having a trouble with
the iterator invalidation. However, looking at other peephole optimizers
passes, I couldn't see how to do this:
#define BUILD_INS(opcode, new_reg, i) \
BuildMI(*MBB, MBBI, MBBI->getDebugLoc(), TII->get(X86::opcode)) \
.addReg(X86::new_reg, kill).addImm(i)
for
2014 Dec 08
2
[LLVMdev] Virtual register problem in X86 backend
Hi,
I'm having trouble using virtual register in the X86 backend.
I implemented a new intrinsic and I use a custom inserter. The goal of
the intrinsic is to set the content of the stack to zero at the end of
each function.
Here is my code:
MachineBasicBlock *
X86TargetLowering::EmitBURNSTACKWithCustomInserter(
MachineInstr *MI,
MachineBasicBlock
2004 Jun 17
2
[LLVMdev] ConstantInt::getRawValue
Is there are reason why ConstantInt::getRawValue method can't be moved one
step into class hierarchy, into ConstantIntegral::getRawValue
The reason I'd like this is that to handle both ConstantInt and ConstantBool,
I need the following:
if (ConstantInt* CI = dyn_cast<ConstantInt>(V)) {
BuildMI(*MBB, IPt, NM::MOVE, 1, Reg).addImm(CI->getRawValue());
} if
2007 Oct 05
6
[LLVMdev] RFC: Tail call optimization X86
On Oct 5, 2007, at 2:42 AM, Arnold Schwaighofer wrote:
> Hi Evan,
> I incoporated the changes you request but to the following i have got
> a question:
>
>> Also, moving the option
>> there will allow us to change fastcc ABI (callee popping arguments)
>> only when this option is on. See Chris' email:
>
> I am not to sure on that. because that would make
2010 Sep 07
1
[LLVMdev] MachineMemOperand and dependence information
Sorry, this is the part in ARMLoadStoreOptimizer.cpp that creates a LDRD
instruction.
Ops.pop_back();
Ops.pop_back();
// Form the pair instruction.
if (isLd) {
MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos,
dl, TII->get(NewOpc))
.addReg(EvenReg, RegState::Define)
2014 Oct 28
2
[LLVMdev] Problem in X86 backend (again)
Hi,
I'm still having problems implementing my custom inserter in the X86 backend.
I found a solution to my last problem (http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-October/078296.html), by using a virtual register.
The binary works when it's compiled in -O0, but not in -O1,-O2,...
I really can't figure what I'm doing wrong... Any idea?
Here is the code of my custom