similar to: llvm-dev not idenitifying me?

Hi Graham, Thanks for your kind explanation. There was internal discussion about it. If possible, can you let me know the Clang/LLVM CodeGen patches for the vector type on phabricator please? I would like to check what kinds of the restrictions the type causes on Clang/LLVM. Thanks, JinGu Kang ________________________________ From: Graham Hunter <Graham.Hunter at arm.com> Sent: 28 May

Hi All, I have read the links from Joel. It seems one of its main focus is vectorization of loop with vector predicate register. I am not sure we need the scalable vector type for it. Let's see a simple example from the white paper. 1 void example01(int *restrict a, const int *b, const int *c, long N) 2 { 3 long i; 4 for (i = 0; i < N; ++i) 5 a[i] = b[i] + c[i]; 6 }

On 09/02/2019 10:44, Aki Tuomi via dovecot wrote: > For some reason mailman failed to "munge from" for senders with dmarc policy ;( > > It's now configured to always munge to avoid this again. I'd say, let Mailman throw all people off the list that have enabled DMARC checking without using exceptions for the lists they are on. It's a known fact that DMARC does not

JinGu: I’m not Graham, but you might find the following link a good starting point. https://community.arm.com/developer/tools-software/hpc/b/hpc-blog/posts/technology-update-the-scalable-vector-extension-sve-for-the-armv8-a-architecture The question you ask doesn’t have a short answer. The compiler and the instruction set design work together to allow programs to be compiled without knowing

On Tue, Oct 1, 2019 at 11:08 AM Graham Hunter <Graham.Hunter at arm.com> wrote: > Hi Luke, hi graham, thanks for responding in such an informative fashion. > > On 1 Oct 2019, at 09:21, Luke Kenneth Casson Leighton via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > typedef vec4 float[4]; // SEW=32,LMUL=4 probably > > static vec4 globalvec[1024]; // vscale ==

In the RISC-V V extension, there is no upper limit to the size vector registers can be in a future CPU. (Formally, the upper limit is at least 2^31 bytes) Generic code can enquire the size, dynamically allocate space, and transparently save and restore the contents of a vector register or registers. On Fri, May 24, 2019 at 11:28 AM JinGu Kang via llvm-dev <llvm-dev at lists.llvm.org>

On 01/03/2015 08:56 AM, Gene Cumm wrote: > On Fri, Jan 2, 2015 at 3:43 PM, Geert Stappers <stappers at stappers.nl> wrote: >> On Sat, Dec 27, 2014 at 05:07:04PM +0100, Geert Stappers wrote: >>> On Mon, Dec 22, 2014 at 11:06:58AM +0200, Ady wrote: >>>>> On Sun, Dec 21, 2014 at 12:21:32PM -0800, Patrick Masotta wrote: >>>>>> [ ... Failed to

On Sat, Jan 3, 2015 at 12:53 PM, John 'Warthog9' Hawley <warthog19 at eaglescrag.net> wrote: > On 01/03/2015 08:56 AM, Gene Cumm wrote: >> On Fri, Jan 2, 2015 at 3:43 PM, Geert Stappers <stappers at stappers.nl> wrote: >>> On Sat, Dec 27, 2014 at 05:07:04PM +0100, Geert Stappers wrote: >>>> On Mon, Dec 22, 2014 at 11:06:58AM +0200, Ady wrote:

On Sat, Jan 17, 2015 at 01:20:58PM -0500, Gene Cumm wrote: > On Sat, Jan 17, 2015 at 12:56 PM, Patrick Masotta wrote: > > On Sat, 2015-01-17 Geert Stappers wrote: > > > If 1 person with a yahoo.com e-mail adres does reply on this > > > message, then we have test result for the setting that was changed > > > wednesday. > > > > test > > Patrick,

Dear all, I have re-written the proposal for interfacing user provided vector functions, originally posted in both llvm-dev and cfe-dev mailing list: "[RFC] Expose user provided vector function for auto-vectorization." The proposal looks quite different from the original submission, therefore I took the liberty to start a new thread. The original thread generated some good

On 8 December 2016 at 18:11, Tian, Xinmin via llvm-dev <llvm-dev at lists.llvm.org> wrote: > For name mangling, we have to follow certain rules of C/C++ (e.g. prefix needs to _ZVG ....). David Majnemer who is the owner and stakeholder for approval for Clang and LLVM. Also, we need to pay attention to GCC compatibility. I would suggest you look into how GCC VectorABI can be extended

I agree with Simon. This looks good conceptually. I have minor implementation comments but that can wait till the code reviews. Sorry for the delay and thanks for working on this. Get Outlook for Android<https://aka.ms/ghei36> ________________________________ From: Simon Moll <moll at cs.uni-saarland.de> Sent: Monday, June 17, 2019 10:02:58 AM To: Francesco Petrogalli; LLVM

Hi Alex, We've only recently managed to get the core scalable vector IR type into the codebase (so it will be present in 9.0); that allows you to write IR with scalable vector types, but there's no backend able to generate code for it yet, and as you mention no support for stepvector (or vscale). Arm will start upstreaming those soon. -Graham > On 13 Jul 2019, at 14:32, Alex Susu via

Hi all, There's a good chance that the people who most need to see this won't see it, but here goes anyway. Google is currently dropping a _lot_ of the mail we attempt to deliver to lists.fd.o subscribers. The immediate cause is sending on mail from domains with SPF/DKIM/DMARC policies which explicitly specify that lists.fd.o cannot relay mail on their behalf. Every time we do that, not

I had a phone conversation yesterday with Graham, Francesco, and Kristof. There is one more reason to go with the native type change: ARM has already written the code with the SV types, and they have patches ready to be reviewed and integrated in LLVM. As I don't want to stand in the way of getting SVE in LLVM as soon as possible, I will also support the integration of the existing patches

I just got this On 9 Feb 2019, at 00:00, dovecot-request at dovecot.org wrote: > Your membership in the mailing list dovecot has been disabled due to > excessive bounces The last bounce received from you was dated > 02-Feb-2019. You will not get any more messages from this list until > you re-enable your membership. You will receive 1 more reminders like > this before your

On Sunday, January 4, 2015 12:53 PM, Geert Stappers <stappers at stappers.nl> wrote: > On Sun, Jan 04, 2015 at 03:14:51PM +0100, Geert Stappers wrote: > > > dmarc_moderation_action (privacy): Action to take when anyone posts > > > to the list from a domain with a DMARC Reject/Quarantine Policy. > > > > > > Wrap Message -- applies the

>In all cases, the IR type of the parameters in `foo` is i64, therefore is not possible to distinguish what C type generated the signature of `foo`. Ouch. >I don’t know if this is going to be a problem for other architectures I haven't checked what IA-32/Intel64 should do for type 2, but I fully agree that this needs to be done properly according to the ABI. >Therefore, I would

Hi, Here's the updated RFC for representing scalable vector types and associated constants in IR. I added a section to address questions that came up on the recent patch review. -Graham =================================================== Supporting Scalable Vector Architectures in LLVM IR =================================================== ========== Background ========== *ARMv8-A

On 17 March 2017 at 16:34, Hal Finkel <hfinkel at anl.gov> wrote: > In general, this is true everywhere. In a large vectorized loop, this cost > may well be worthwhile. The idea is that the cost model should account for > all of these costs. If it doesn't properly, we should fix that. Isn't this only worth when the SIMD instructions can be conditionalised per lane? I