Displaying 20 results from an estimated 400 matches similar to: "ShuffleKind SK_ExtractSubvector"
2015 Jan 14
6
[LLVMdev] Instruction Cost
Hi,
I'm looking for APIs that compute instruction costs, and noticed several of
them.
1. A series of APIs of TargetTransformInfo that compute the cost of
instructions of a particular type (e.g. getArithmeticInstrCost and
getShuffleCost)
2. TargetTransformInfo::getOperationCost
3. CostModel::getInstructionCost::getInstructionCost in
lib/Analysis/CostModel.cpp
Only the first one is used
2015 Jan 15
2
[LLVMdev] Instruction Cost
CostModule::getInstructionCost also consults TTI (
http://llvm.org/docs/doxygen/html/CostModel_8cpp_source.html#l00380). No?
Jingyue
On Wed, Jan 14, 2015 at 4:05 PM, Chandler Carruth <chandlerc at google.com>
wrote:
>
> On Wed, Jan 14, 2015 at 3:54 PM, Jingyue Wu <jingyue at google.com> wrote:
>
>> I'm looking for APIs that compute instruction costs, and noticed
2010 Apr 20
2
[LLVMdev] SplitVectorOp from CopyFromReg
Hello,
I have a kernel that's swizzling a vector inside a loop. The vector was
created before the loop. The first node in the dag is an extract subvector
which calls into SplitVectorOp. The issue is that the node passed to it
comes from a CopyFromReg and SplitVectorOp doesn't know what to do. Is
there a reason why SplitVectorOp doesn't handle CopyFromReg nodes? If not,
can I submit a
2009 Dec 03
0
[LLVMdev] Selecting Vector Shuffle of Different Types
On Wed, Dec 2, 2009 at 3:46 PM, David Greene <dag at cray.com> wrote:
> The AVX saga continues.
>
> I am attempting to write a pattern for VEXTRACTF128 but am having some
> problems. My attempt looks something like this:
>
> defm EXTRACTF128 : avx_fp_extract_vector_osta_node_mri_256<0x19, MRMDestReg,
> MRMDestMem, "extractf128", undef,
2010 Apr 20
0
[LLVMdev] SplitVectorOp from CopyFromReg
Hi Javier,
> I have a kernel that's swizzling a vector inside a loop. The vector was
> created before the loop. The first node in the dag is an extract subvector
> which calls into SplitVectorOp. The issue is that the node passed to it
> comes from a CopyFromReg and SplitVectorOp doesn't know what to do. Is
> there a reason why SplitVectorOp doesn't handle CopyFromReg
2009 Dec 02
5
[LLVMdev] Selecting Vector Shuffle of Different Types
The AVX saga continues.
I am attempting to write a pattern for VEXTRACTF128 but am having some
problems. My attempt looks something like this:
defm EXTRACTF128 : avx_fp_extract_vector_osta_node_mri_256<0x19, MRMDestReg,
MRMDestMem, "extractf128", undef, X86f32, X86i32i8,
// rr
[(set VR128:$dst,
2018 Apr 10
1
64 bit mask in x86vshuffle instruction
Please tell me whether the following implementation is correct.....
My target supports 64 bit mask means immediate(0-2^63)
I have implemented it but i dont know whether its correct or not. Please
see the changes below that i have made in x86isellowering.cpp
static SDValue lower2048BitVectorShuffle(const SDLoc &DL, ArrayRef<int>
Mask,
MVT VT,
2008 Jan 07
3
Seeking a more efficient way to find partition maxima
Hi.
Suppose I have a vector that I partition into disjoint, contiguous subvectors. For example, let v = c(1,4,2,6,7,5), partition it into three subvectors, v1 = v[1:3], v2 = v[4], v3 = v[5:6]. I want to find the maximum element of each subvector. In this example, max(v1) is 4, max(v2) is 6, max(v3) is 7. If I knew that the successive subvector maxima would never decrease, as in the example,
2013 Mar 05
4
[LLVMdev] Vector splitting vs widening
Hello,
Working on my (currently out-of-tree) BG/Q PPC enhancements, I've run into the following problem with vector type legalization. Here's a quick example:
Scalarize node result 0: 0x2348420: v1f32 = extract_subvector 0x23434a0, 0x2348320 [ID=0]
Scalarize node result 0: 0x2348220: v1f32 = extract_subvector 0x23434a0, 0x23466e0 [ID=0]
Split node result: 0x23469e0: v4f32 =
2013 Mar 05
0
[LLVMdev] Vector splitting vs widening
Hi Hal,
On 05/03/13 18:50, Hal Finkel wrote:
> Hello,
>
> Working on my (currently out-of-tree) BG/Q PPC enhancements, I've run into the following problem with vector type legalization. Here's a quick example:
>
> Scalarize node result 0: 0x2348420: v1f32 = extract_subvector 0x23434a0, 0x2348320 [ID=0]
>
> Scalarize node result 0: 0x2348220: v1f32 = extract_subvector
2018 Apr 09
1
llvm-dev Digest, Vol 166, Issue 22
Hi Krzysztof,
Sure, please see below. DAG.dump.() before and after, annotated with what I
believe the DAG means.
I've spent some time debugging the method but it's proving difficult to
determine where the logic is misfiring. Disabling the entire combine causes
a lot of failing x86-64 tests - I may have to learn an upstream vector ISA
to make progress on this.
Thank you
>From your
2009 Aug 25
3
Regular expression to define contents between parentheses
Hello dear R-helpers,
I haven't been able to figure out of find a solution in the R-help archives about how to delete all the characters contained in groups of parenthesis. I have a vector that looks more or less like this:
myvector<-c("something (80 km/h, sd) & more (6 kg/L,sd)", "somethingelse (48 m/s, sd) & moretoo (50g/L , sd)")
I want to extract all
2016 Jun 02
4
[GSoC 2016] Parameters of a target architecture
Dear LLVM contributors,
I work on the "Improvement of vectorization process in Polly". At the
moment I'm trying to implement tiling, interchanging and unrolling of
specific loops based on the following algorithm for the analytical
modeling [1]. It requires information about the following parameters
of a target architecture:
1. Size of double-precision floating-point number.
2.
2020 Nov 05
4
[Proposal] Introducing the concept of invalid costs to the IR cost model
Hi,
I'd like to propose a change to our cost interfaces so that instead of returning
an unsigned value from functions like getInstructionCost, getUserCost, etc., we
instead return a wrapper class that encodes an integer cost along with extra
state. The extra state can be used to express:
1. A cost as infinitely expensive in order to prevent certain optimisations
taking place. For example,
2018 Apr 09
2
A way to opt out of a dag combine?
Is there an established way of disabling a DAG combine on a per target
basis, where it appears to be detrimental to the generated code? Writing if
(!mytarget) in DAGCombiner.cpp works but tends to be erased by git merge
and generally doesn't look ideal. Writing the inverse transform in target
specific code doesn't work in this instance and in general creates an
infinite loop.
Guidance
2014 Jul 17
4
[LLVMdev] Using CostModel to estimate machine cycles of each instruction
There is CostModel.cpp since LLVM3, I am wondering if anyone can give me
an concrete example on how to use this pass to estimate cycles used in a
given IR file.
Thank you very much.
Don
2010 Mar 30
1
[LLVMdev] Question on SelectionDAGBuilder
I ran into some odd code being generated today and I came
across something that doesn't look quite right.
In SelectionDAGBuilder::visitShuffleVector there's some code to see if we can
convert the shuffle to an EXTRACT_SUBVECTOR. After computing min/max
values of the mask for each operand, there's a look that looks at the ranges
and determines whether an EXTRACT_SUBVECTOR can be used:
2009 Apr 17
1
matching subvectors in vector sets
Hi,
I've got a list of ~20000 elements that look like this:
[1]
"A00096:A00096:A00096:A00096:A02178:A02178:A07776"
[2]
"A00046:A00076:A01101:A04146:A05671:A07169"
[3]
"A00038:A00932:A02185:A02370:A02818:A02818:A02818:A02818:A04732:A07142:A07142"
[4]
"A00096:A01352:A01352:A02023:A05001:A05001:A07776"
[5]
2007 Feb 01
3
Can this loop be delooped?
Hi.
I have the following code in a loop. It splits a vector into subvectors of
equal size. But if the size of the original vector is not an exact multiple
of the desired subvector size, then the first few subvectors have one more
element than the last few. I know that the cut function could be used to
determine where to break up the vector, but it doesn't seem to provide
control over
2010 Sep 19
1
Weibull- Random Censoring
I generate random vector from Weibull distribution
sampWB <-urweibull(sampleSize, shape=shape.true, scale=scale.true, lb=0, ub=Inf)
how can I create subvector containing 30% of samplesize of sampWB which should be assigned as Censored data?
The probability for each value in sampWB can be uniform to be included in the subvector.