similar to: MC PowerPC 32 bit vs. 64 bit

> But where is the flat set? Maybe I can debug and check what is going on. The MCInstrDesc are in a table in lib/Target/PowerPC/PPCGenInstrInfo.inc of your build directory. > Some additional information: > > MCInst opcode: 0x7cb > Decode Index: 0x1e I had assumed this would have dissembled to '// Inst #234 = BC' which does have the branch flag set, but I think that

The `isBranch` flag is already set on the branch instructions. Furthermore, we do use the `isBranch()` query in a few places in the PPC back end, so this does work. Perhaps there's something specific about the lldb usage? Is it somehow possible that the `isBranch()` query is called on the wrong instruction? Would you be able to provide a test case that reproduces the issue? On Thu, Nov 30,

Dear Community, I would like to discuss few points to use RDF to extend register remat scope. Mr. Krzysztof and I have started discussion this on private mail. But I think now it would be better to include community. Interested community member kindly previous discussion (at the end of mail) before starting here. After analyzing if RDF can be used for solving Remat, we think that problem with

Hi, I'm considering to use MC disassembler for ARM target in a binary translation project. However after trying some ARM binary and I find that there are a lot of instructions that the disassembler fails to to decoding. Could anyone give me some information about the maturity of ARM disassembler? Thanks! David -------------- next part -------------- An HTML attachment was scrubbed... URL:

I believe I have now fixed the 0x64 0xa1 0x00 0x00 0x00 0x00 bug in r199364. On Wed, Jan 15, 2014 at 10:53 AM, Craig Topper <craig.topper at gmail.com>wrote: > To fix it we need to change offset8/offset16/etc to have two suboperands > and update the printer to understand that. Also update the disassembler to > add the segment to the MCInst when its creating it. When I did these

On Jun 5, 2012, at 7:44 PM, Fan Dawei <fandawei.s at gmail.com> wrote: > Hi, > > I'm considering to use MC disassembler for ARM target in a binary translation project. However after trying some ARM binary and I find that there are a lot of instructions that the disassembler fails to to decoding. > > Could anyone give me some information about the maturity of ARM

Hi, It seems LLVM-MC is broken with Avx512? $ echo "vinserti32x4 \$1, %xmm21, %zmm5, %zmm17"|./Release+Asserts/bin/llvm-mc -assemble -arch=x86-64 -show-encoding -x86-asm-syntax=att .text vinserti32x4 $1, %xmm21, %zmm5, %zmm17 # encoding: [0x62,0xa3,0x55,0x48,0x38,0xcd,0x01] $ echo "0x62,0xa3,0x55,0x48,0x38,0xcd,0x01" |./Release+Asserts/bin/llvm-mc -disassemble

Hi Evan, Thanks for the information! I've try to use llvm-objdump to disassemble some ARM binary, such as busybox in android. ./llvm-objdump -arch=arm -d busybox There are many instructions cannot decode, :./llvm-objdump: warning: invalid instruction encoding Did I use llvm-objdump in a correct way? I think that one possible reason is that llvm-objdump encounter pc relative data.

Hi David, > I've try to use llvm-objdump to disassemble some ARM binary, such as busybox > in android. > > ./llvm-objdump -arch=arm -d busybox It's probably assuming the wrong architecture revision. I don't have an android busybox handy, but I see similar on binaries compiled for ARMv7. The trick is to use: llvm-objdump -triple=armv7 -d whatever (ARMv7 covers virtually

Hi everyone, Rafael has graciously given me some pointers for helping out on the ARM/MC .s emission infrastructure, and I am volunteering to do so. It looks like as of yesterday, the MC obj emitter for ARM is also incomplete (there does not seem to be a ARMMCCodeEmitter.cpp, for example) So if anyone already has started looking into this, I'd like to pool info so as to not step on toes. Any

Hi Jason, I've just started actively working on this. Coordinating to get things moving even faster sounds great! Can you elaborate a bit on your ultimate goals and use cases are? That might help us better determine a natural breakdown and separation of tasks. Evan and Chris may have suggestions there, too, as I know they're both very interested in getting this stuff fleshed out and

I'm wondering if anyone is working on a machine code -> LLVM bitcode disassembler? Obviously, there won't be a one-to-one correspondence but it seems like you should be able to get close. There's always inline asm for the remaining fragments. So is there such a thing? Thank you, Bob

On Fri, Aug 25, 2017 at 8:51 AM, Daniel Sanders <daniel_l_sanders at apple.com> wrote: > (removed my @imgtec.com address since it no longer exists) > > Sorry for the slow reply, it's a busy time for me right now. > > > On 23 Aug 2017, at 00:21, George Karpenkov via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > > > Hi, > > > > As a

Well, you’ll probably need to specify which CPU for the instructions to be recognized as valid encodings. -mcpu=knl doesn’t seem sufficient, though, so there’s probably something more going on. Elena, do you know what’s happening here? It’s important that the disassembler work with the new instructions as well as the assembler. I looked but didn’t see any disassembler tests for avx512. -Jim On

I've been working on adding support for a (semi-proprietary) extension for PowerPC called "Paired-Singles". It's a SIMD instruction set supporting various operations on a vector of 2 32-bit floating point numbers. The Extension is found in the PowerPC 750CL, modified variants of it are used in the Nintendo GameCube (Gekko), the Nintendo Wii (Broadway) and the Nintendo Wii U

On Tue, 2014-01-14 at 22:59 -0800, Craig Topper wrote: > I started trying to fix this tonight but it's pretty nasty to fix. > I'll try to make another go at it later this week. Much of it seems fixed already; what's left to fix? The segment prefix override? Does that mean we get to fix disassembly of '0x65 0xa4' while we're at it? (Although we can't even

I suspect this is a straight forward problem so I thought I'd ask. I'm developing a new backend. I recently updated from the LLVM repository and now my output assembly is branching to labels/blocks that have been removed. It had been working fine two weeks ago. What looks suspicious is the following message: TryTailMergeBlocks: BB#1, BB#3, BB#4 Looking for common tails of

I"m getting build errors I think from one of your patches O tjoml. You need to have a build area that builds with clang and does warnings as errors to avoid these issues on putback. here is my configure step for example: /home/rkotler/llvm_trunk/configure --enable-werror --prefix=/home/rkotler/ll vm/install CC=/home/rkotler/llvm_3_2/install/bin/clang CXX=/home/rkotler/llvm_3_

Hello Developers, I am working with my other batchmates to improve register remat in LLVM. We want to remat live ranges made of multiple instruction. Just to support our proposal here is a simple example that currently remat does not cover $ cat ~/tmp/tl.c void foo(long); void bar() { for (int i = 0; i < 1600; ++i) foo(3494348345984503943); } $ clang -O3 -S -o - ~/tmp/tl.c -target

It is r195843 and fixed in r195905, FYI. 2013/11/29 Reed Kotler <rkotler at mips.com>: > I"m getting build errors I think from one of your patches O tjoml. > > You need to have a build area that builds with clang and does warnings as > errors to avoid these issues on putback. > > here is my configure step for example: > /home/rkotler/llvm_trunk/configure