similar to: Generate Register Indirect mode instruction

Displaying 20 results from an estimated 20000 matches similar to: "Generate Register Indirect mode instruction"

2020 Jul 14
2
[Beginner] Understanding Tablegen language
On 7/13/2020 21:30, Thomas Lively via llvm-dev wrote: > Part of the problem is that ISel patterns are like their own DSL inside > the TableGen DSL, so keywords like "ins", "outs", and "ops" aren't > keywords at the TableGen level, but rather at the level of the ISel > system implemented with TableGen. Copying existing patterns and reading > the
2016 Oct 12
2
Generate Register Indirect mode instruction
On 10/12/2016 2:22 PM, Alex Bradley wrote: > > > > You probably want to look at the x86 backend; it has a lot of > instructions which involve both computation and memory. Take the > following IR, a variant of your example: > > > > define void @foo(i32 *%a, i32 *%b, i32 *%c) { > > entry: > > %0 = load i32, i32* %a, align 4 > > %1 = load i32,
2019 May 13
3
How to change CLang struct alignment behaviour?
Hi Joan, On Mon, 13 May 2019 at 18:01, Joan Lluch <joan.lluch at icloud.com> wrote: > After looking at it a bit further, I think this is a Clang thing. Clang issues “align 2” if the struct has at least one int (2 bytes), but also if the entire struct size is multiple of 2. For example a struct with 4 char members. In these cases the LLVM backend correctly creates word sized load/stores
2017 Dec 01
2
Some strange i64 behavior with arm 32bit. (Raspberry Pi)
Hi Tim, thanks for the swift response! @debug is defined in the same module, which makes this all the more confusing. The target information from the working example are: target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target triple = "armv6kz--linux-gnueabihf" from the ghc produced module: target datalayout =
2017 Nov 17
2
Ensuring that dead allocations from a custom allocator are killed by LLVM
Hello all, I have a custom allocator, and would like to teach LLVM about its semantics. In particular, I would like LLVM to kill allocations that are "dead", similar to dead new in C++. Consider this example: ; ModuleID = '<stdin>' source_filename = "Module" ; Function Attrs: inaccessiblememonly noinline norecurse nounwind declare i8* @alloc(i64)
2019 Feb 25
3
Why is there still ineffective code after -o3 optimization?
Hi, I have some IR module from random generation (mostly ineffective instructions). It has a function with void return, and two function arguments where one is a reference. Therefore, I expect every instruction not altering the value at the 2nd arguments address should be ineffective. Here is the function definition (see below for full ll): define void @_Z27entityMainDataInputCallbackdRd(double
2020 Jul 13
2
[Beginner] Understanding Tablegen language
Hi, I am new to LLVM and I find TableGen language really cryptic. The reference manual to the language is not helpful either. I can look at the existing .td file and reverse engineer but I am looking for a detailed manual. Specifically, I have below questions: 1. What is a basic syntax for writing a dag? From the lang ref manual I can see that its something like operator followed by ArgList which
2020 Jul 11
3
Bug in pass 'ipsccp' on function attribute 'argmemonly'?
Hi all, Let's see an example (from Alexandre Isoard) first: **************************************************************************************** ; RUN: opt -ipsccp -deadargelim -licm -O2 -S < %s @g = internal global i32 0 ; Function Attrs: argmemonly define internal void @foo(i32* nonnull dereferenceable(4) %arg, i32 %val) #0 { entry: store i32 %val, i32* %arg ret void } define
2020 Sep 09
3
constrained cosine rounding mode behavior
Hi: I am trying to implement interval arithmetic through llvm. I have a problem with the rounding mode with llvm.experimental.constrained.cos I have two pieces of codes: ; Function Attrs: norecurse nounwind readnone ssp uwtable define double @cosine_down(double returned) local_unnamed_addr #0 {   ; call the llvm intrinsic to perform downward cosine
2020 Jul 14
3
Bug in pass 'ipsccp' on function attribute 'argmemonly'?
Thank you Hal and Stefan! Bug report is filed: https://bugs.llvm.org/show_bug.cgi?id=46717 And Stefan, I think 'attributor' is a really nice pass, and can infer more precise and useful attributes, which may give more opportunities for optimization. But we shouldn't depend on 'attributor' to correct wrong function attributes, because we cannot run 'attributor' after
2016 Oct 17
2
Generate Register Indirect mode instruction
I was under the impression his answer was correct from your reply, no? On Oct 17, 2016 17:45, "Alex Bradley via llvm-dev" <llvm-dev at lists.llvm.org> wrote: > Gentle Ping !! > > I would appreciate any help on this. I want to generate following as > described by Krzysztof : > > %v1 = load i32, i32* %a > %v2 = load i32, i32* %b > %v3 = add i32 %v1, %v2 >
2019 Jun 11
3
How to tell LLVM to treat Commutable library calls as such, for example multiplication?
A few library calls are commutable by definition, for example multiplications. I defined them as LibCalls for my architecture. However, I found that arguments are always passed in the order they are generated by Clang thus missing possible optimisations. For example, the following IR code ; Function Attrs: minsize norecurse nounwind optsize readnone define dso_local i16 @multTest(i16 %a, i16
2020 May 27
4
default behavior or
Hi Devs, going by this link https://llvm.org/docs/LangRef.html#floatenv it says that floating point operation does not have side effects by defaults. but when compile a test case i.e. cat a.c float foo(float a, float b) { return a+b; } $clang a.c -O2 -S -emit-llvm emit ir like: $cat a.ll --------------------------------------- ; ModuleID = 'a.c' source_filename = "a.c" target
2019 Sep 30
3
[cfe-dev] CFG simplification question, and preservation of branching in the original code
On Mon, Sep 30, 2019 at 11:52 AM Joan Lluch <joan.lluch at icloud.com> wrote: > > Hi Roman, > > Is "test" actually an implementation of a 64-bit-wide multiplication > compiler-rt builtin? > Then i'd think the main problem is that it is being optimized in the > first place, you could end up with endless recursion… > > > No, this is not a compiler-rt
2016 Oct 14
2
Generate Register Indirect mode instruction
> If I understand correctly: > > %v1 = load i32, i32* %a > %v2 = load i32, i32* %b > %v3 = add i32 %v1, %v2 > store i32 %v3, i32* %c > > maps to (using invented mnemonics): > > ASSIGN R0, %a > ASSIGN R1, %b > ASSIGN R2, %c > ADD *R2, *R0, *R1 > > I.e. pattern > (store %c, (add (load %a), (load %b))) > becomes > (ADD (ASSIGN R2, %c), (ASSIGN
2016 Oct 12
2
Generate Register Indirect mode instruction
On 10/12/2016 3:15 PM, Alex Bradley wrote: > > Yes the result goes into memory. But the *address* of that destination > memory location also needs to be loaded first into a register. > Your architecture has a single instruction for the following operation? define void @foo(i32 **%a, i32**%b) { entry: %l1 = load i32*, i32** %a, align 4 %l2 = load i32, i32* %l1, align 4 %l3 =
2019 Oct 01
5
PR43374 - when should comparing NaN values raise a floating point exception?
Hi, I’ve been investigating https://bugs.llvm.org/show_bug.cgi?id=43374, which is about clang/llvm producing code that triggers a floating point exception when x is NaN, when targeting ARM, in the below code example. int bar(float x) { return x!=x ? 0 : 1; } The C99 standard states in section 7.12.14: """ The relational and equality operators support the usual mathematical
2019 Sep 30
2
[cfe-dev] CFG simplification question, and preservation of branching in the original code
For the MSP430 example, I'm guess its InstCombiner::transformSExtICmp or InstCombiner::transformZExtICmp ~Craig On Mon, Sep 30, 2019 at 2:21 PM Support IMAP <support at sweetwilliamsl.com> wrote: > Hi all, > > Ok, I just found a much simpler example of the same issue. > > Consider the following code > > int cmpge32_0(long a) { > return a>=0; > } >
2020 Jun 28
2
__restirct ignored when including headers like <cmath>
Hi, I am observing a strange behaviour in which Clang ignores __restirct when I include some standard headers. For example, this code: void vec_add(int* __restrict a, int* __restrict b, int n) { #pragma unroll 4 for(int i=0; i<n; ++i) { a[i] += b[i]; } } results in: ; Function Attrs: nofree norecurse nounwind define dso_local void @_Z7vec_addPiS_i(i32*
2017 Mar 09
5
What is ConstantExpr?
Hi, All. Does anybody know about ConstantExpr in llvm? What's it? Since it always appears after llvm optimization such as -O2 level, what is it supposed to be to codegen? I am wondering it represents constant value which can be determined or computed at compile-time(actually is link-time) to improve performance. Although we do not know the actual constant value util the object file is linked.