similar to: LLVM z80 backend and llvm-dis missing?

I'm working on a Z80 backend and am trying to efficiently lower SEXT, specifically 8 to 16 bit, in LowerOperation() according to the following rules: The Z80 has 8 bit registers and 16 bit registers, which are aliased versions of two 8 bit registers. 8 bit registers are named A, H, L, D, E and some more. 16 bit registers are HL (composed of H + L), DE (D + E) - and some more - with L and

Hello. I am playing with LLVM and trying to make Z80 (Zilog Z80) backend. The source code is attached. I have succesfully made some simple test. But now I have problem with ADD instruction. The source C code is: typedef struct { unsigned char id1; unsigned char id2; unsigned char id3; } testS; void simple() { testS test; test.id1 = 0x40; test.id2 = 0x80; test.id3 = 0xc0; } It

Hi Peter, I think the problem is that you did not explicitly define stack alignment in Z80TargetMachine.cpp DataLayout("e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8-n8") Try to add S16 to the string if your stack is 2-byte aligned. Refer to http://llvm.org/docs/LangRef.html#datalayout . If it does not work, try to specify the layout in the input module using target layout directive. David On

Hello. I have played with DataLayout and found a solution with is uknown to me. I added S16 and also s0:16:16, but it had not worked. Then I found that in Z80FrameLowering.h I am calling TargetFrameLowering with stack aligment set to 8. So I changed it to 2 bytes. But this also didn't help. Then I changed llc to show TargetDataLayout and found that a option is set to a0:0:64. So I changed

Yes, such optimizations are something for the "last 20%" of the project, nice to have's. As of now, I have yet to get a feeling of what LLVM can do on its own, depending on what it's from the instruction tables and where it needs help, and how much in other processing stages. As this affects the way how the instruction info table will be set-up, I appreciate your suggestions

>It should be possible to get llvm to produce very good code for the Z80... Yes, I was thinking that too. These techniques didn't exist back then, so I'm really looking forward to the point where the first regular C sources can be compiled and see the magic happening in action live :) ------------------------------------------------------------------------ *From:* Bruce Hoult

Thanks Bruce, and elaborately as ever. Again, I'm surprised about your very thorough Z80 knowledge when you said you only did little on the ZX81 in the eighties :D OK, understood. I was first thinking about doing something like this for small frames: 1. push bc # 1 byte; 11 cycles - part of call frame-cleanup: save scratch register +-----begin call-related 2. ld

Hi Peter, (I'm CC'ing the LLVMdev list as there might be others able to help you) I don't know this assertion, so can't help you with that particular problem. But concerning "more debug info": Do you know the following two links? http://llvm.org/releases/3.0/docs/ProgrammersManual.html#DEBUG You can find some example debug code e.g. in method Select(SDNode *Node) in

Hi All. I'm writing storeRegToStackSlot and loadFromStackSlot function for my Target. This Target can store/load one byte (not all word) from FrameIndex. If I need to store 16 bit register I will must to split it to two instruction like this: BuildMI(MBB, MI, dl, get(Z80::LD8xmr)) .addFrameIndex(FrameIndex).addImm(0) .addReg(SrcReg, 0, Z80::subreg_lo); BuildMI(MBB, MI, dl,

Hi Dmitriy, As you've seen our current spill code assumes that spill/reloads are single instructions. I think the best way to work around this is to introduce load/store pseudo-instructions and expand these after register allocation. Cheers, Lang. On Sat, Feb 23, 2013 at 12:15 AM, Dmitriy Limonov <earl at excluzive.ws> wrote: > Hi All. > > I'm writing

Hi, I'm trying to revive jacobly0's Z80 back-end (from https://github.com/jacobly0/llvm-z80) and build it with a current version of LLVM. Apart from some interface changes, I'm stuck at building the tables. Specifically, the generation of the DAG instruction selector causes an assertion in the table generator: Assertion failed: Ops.size() >= NumSrcResults &&

I want to make Z80 codegen backend to the LLVM. CLang+LLVM looks perfect, while quick playing around. Some questions available: 1) Does LLVM support to generate "mixed" code ? For example: in microcontrollers world the subroutine call with const arguments may be decorated like this: call subroutine defw wArg1 defw wArg2 ; ordinary code continues here subroutine pop return address

For a Z80 backend, "eliminateCallFramePseudoInstr()" shall adjust the stack pointer in three possible ways, e.g. after a function call, depending on the amount (= adjustment size) *and some other rules*: 1. via one or more target "pop <reg>" instructions (SP increments +2 per instruction), using an unused reg (disregarding the contents after the operation), followed

I'm working on defining the instructions and implementing the lowering code for a Z80 backend. For now, the backend supports only the native CPU-supported datatypes, which are 8 and 16 bits wide (i.e. no 32 bit long, float, ... yet). So far, a lot of the simple stuff like immediate loads and return values is very straightforward, but now I got stuck with ISD::TRUNCATE, as in:

Hello. I write backend for Z80 cpu and I have some trouble with lowering load/store nodes to different machine opcodes. Some target instructions work with specified registers (not all registers in RegisterClass). Often it's one or two registers. I don't understand how use ComplexPattern in this case. But if I don't use ComplexPattern I'll have other problems - not all

I received a sample IP/Speakerphone from my friends in China today. Asterisk setup was fairly uncomplicated and I had it running as an extension on my server within a few minutes. Sounds quality of both the receiver and the speakerphone are fine (wife's opinion). Are there any tests I should run with this phone? Following are the specs: - Single line appearance - Alpha display, 2x16 chars -

This is a question about optimizing the code generation in a (new) Z80 backend: The CPU has a couple of 8 bit physical registers, e.g. H, L, D and E, which are overlaid in 16 bit register pairs named HL and DE. It has also a native instruction to load a 16 bit immediate value into a 16 bit register pair (HL or DE), e.g.: LD HL,<imm16> Now when having a sequence of loading two 16

On RH 5.2, and I've previously compiled and installed 3.0.28a on this box. configure ran clean, but make fails with:- Compiling smbd/server.c Linking bin/smbd smbd/server.o: In function `housekeeping_fn': server.c:(.text+0x21e): undefined reference to `attempt_machine_password_change' collect2: ld returned 1 exit status make: *** [bin/smbd] Error 1 Anyone else encountered this?

On 12/13/2008, Dave McGuire (mcguire at neurotica.com) wrote: > My network security is handled elsewhere. I too believe in layered > security, but my desire to use the right tool for the job is much > stronger. My mail server is busy serving mail; my network security > is handled by equipment built and optimized for that job. Firewalls don't add any (perceptible) extra work or