similar to: Spill code

Yes, I have done exactly the same. The wawanalyzer is the same. I changed ARM.h and ARMTargetMachine.cpp in the tager/arm folder. then I make tool/llc and lib folder. On Tue, Nov 17, 2015 at 10:55 AM, John Criswell <jtcriswel at gmail.com> wrote: > On 11/17/15 12:16 AM, fateme Hoseini via llvm-dev wrote: > > Hi, > So, I run my pass in X86 target with llc command and it printed

Hi, So, I run my pass in X86 target with llc command and it printed out "hello****". Now I am trying to do the same pass for ARM target. So I did exactly what I did for X86 as mentioned in my previous posts. When I run the following command: llc -march=arm test.ll -o test nothing prints out. I did the same for MIPS target too and I got no result. Can anyone tell me what I'm doing

Hi, Is there a way to get instruction's offset at compile time with llvm for ARM? I am trying to create a map between instructions at compile time and this run-time info. Since PC is a relative value, I am trying to use the instruction's offset as a constant property of instruction to create this map. I think offset information should be available to create the executable, if so where to

Hello everybody, hi Evan, this patch changes the lowering of arguments for tail call optimized calls. Before arguments that could be overwritten by each other were explicitly lowered to a stack slot, not giving the register allocator a chance to optimize. Now a sequence of copyto/copyfrom virtual registers ensures that arguments are loaded in (virtual) registers before they are lowered to the

Thank you so much. That helped alot. Fami On Wed, Nov 4, 2015 at 9:40 AM, John Criswell <jtcriswel at gmail.com> wrote: > On 11/3/15 7:54 PM, fateme Hoseini wrote: > > Dear John, > Thank you so much for your help. I looked at those documents. Could you > kindly answer the following questions: > > Does it mean that I have to make my own backend target in order to write

Dear Tim, Thank you for your thorough reply. So, based on your reply I get every operand and check them to be (isDef && !isimplicit). Now my problem is that it gives me the physical register number.i.e, for example, instead of r0, it return %physreg66. Could you please help me on how to convert these physical register number to the ARM related register? I mean the 15 GPRs in ARM. Thank

Hello everyone, I am trying to add checkpoints to my IR code. In order to do that I need to add this instruction: call void @m5_checkpoint(i64 0, i64 0) to some of the basic blocks in my benchmark. m5_checkpoint is a function defined for checkpointing in another simulator and is not included in my benchmark source code. So I need to create this instruction and I couldn't figure out how to do

Dear John, Thank you so much for your help. I looked at those documents. Could you kindly answer the following questions: Does it mean that I have to make my own backend target in order to write a machine pass even if I want to run a simple machinefunction pass? for example,if I want my pass to get MIPS instructions as an input, I have to copy all the files from mips target and add a file to it

For my target, I handle incoming memory arguments by creating a store to memory (in LowerCall, [1]), then creating a fixed object on the stack and loading from it (in LowerFormalArguments[2]). This approach was based on MSP430. I now have the problem that the resulting loads in my output assembly are done assuming that the call stack looks something like: ------ MemArg ------ MemArg ------

Hi Does LLVM dynamically run the program to obtain profiling information like branch weight? if so, can we access the information regarding this run like the number of instructions that have been executed dynamically between two specific points of the program? Thanks -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hello everyone, I am trying to write a code to do the following: 1. Get an ARM machine instruction 2. Find destination register of that instruction that has been written 3. set a bit in a vector, according to that register number. (Since it's ARM, I have a 15 bit vector) It means if I have : add r0, r1, r0 I want to get r0 as dest reg and set the index 0 of my vector to 1. I get my machine

Hi everyone, I am a new commer and I 'm tying to use LLVM to cross compile a code. I want to cross compile to MIPS and the host is the default x86. The more I read the document the more confused I get. I see documents on cross-compiling to ARM. But some install some gcc packages, while some use clang. I don't know where to start and how to do it. Is this just enough to run a command line

Hi everyone, I am a LLVM newbie. I need to write a machinefunction pass for my project. This should be an analyzer of the machine code to do some profiling. I have written a couple of function passes for front end, but it seems they are completely different. I searched through forum and llvm documents, but couldn't find anything useful or questions were unanswered. Can anyone reference me to

Attached is a patch to print asm comments for spill information. We've discussed the mechanisms before but I wanted to run the patch by everyone before I start to commit pieces. -Dave -------------- next part -------------- A non-text attachment was scrubbed... Name: spillcomments.patch Type: text/x-diff Size: 58930 bytes Desc: not available URL:

Hi all, Sorry to bother those not interested. I am a newbie to LLVM. I have a problem on allocating additional stack slot for checkpointing. However, I have no idea on how to allocate redundant stack slot in llvm. Any suggestions? Thanks, Ray -------------- next part -------------- An HTML attachment was scrubbed... URL:

Ok, I've had time to track this down a little bit more and I seem to have found another case where it fails. This is occurring during Schedulur->EmitSchedule() in SelectionDAGISel.cpp:695. The problem seems to be that somehow the CopyToReg part of the switch statement in ScheduleDAG::EmitNode has a FrameIndex as its second operand. This is especially problematic because the code is either

On Jan 27, 2009, at 3:54 PM, Villmow, Micah wrote: > Ok, I've had time to track this down a little bit more and I seem to > have found another case where it fails. This is occurring during > Schedulur->EmitSchedule() in SelectionDAGISel.cpp:695. The problem > seems > to be that somehow the CopyToReg part of the switch statement in > ScheduleDAG::EmitNode has a

Hello everyone, As I mentioned in my previous posts,I am using a machinefunction pass to find all the loops in the program and do some analysis on them. I have completed my pass now and it works correctly. but the only issue is that,I have noticed that if I have two functions in my program, and one of them is part of the loop for another one ,by using runonmachinefunction(), I will get one loop

Ours is an accumulator based architecture. So one operand of ADD/SUB operations is in REG (accumulator) and the other one is in Memory. The result can be left either in REG or memory. The LLVM DAG for such operations expect both operands in REG. for example: char a, b, c, d, e; a = (b - c) + (d - e); generates addc:i8 (subc:i8(b,c), subc:i8(d,e)) Looks like we need to custom lower addc

Hi llvmdev, I'm trying to figure how llvm remembers stack slots allotted to callee saved registers on x86. In particular, llvm pushes registers in decreasing order of FrameIdxs [1], so the offsets they get (as returned by MFI->getObjectOffset) don't directly correspond to their actual stack locations. In X86FrameLowering's emitCalleeSavedFrameMoves, when emitting DWARF