similar to: [GSoC 2016] Adding MachineModule pass to LLVM

Hi all, I am attempting to implement the "reaching definitions" data-flow algorithm on (X86) MachineBasicBlocks for an analysis pass. To do this, I need to compute gen/kill sets for machine basic blocks. To start with, I am only considering the general-purpose registers, RAX-R15 and their sub-registers. Thus, I need to examine each MachineInstr to determine which register(s) it

Hi all, I am working on creating a MachineFunctionPass to perform an analysis on X86 code. After a bit of trouble, I was able to get my pass compiling and running correctly in llc. However, since a machine pass is compiled directly into the code generator, rerunning "make" across the LLVM build tree involves re-linking most of the major libraries and executables. This is a rather

Hello all, Is there an easy way to get the human-readable opcode mnemonic (e.g., "MOV32ri64", "CMP32ri8", "JLE_1") for a MachineInstr? I am writing a backend analysis pass for security research, where the idea is for a researcher to examine the output of my pass and identify instructions from it for use in an attack. Right now I'm representing unique

*Vivek Pandya* On Fri, Mar 18, 2016 at 10:03 PM, Quentin Colombet <qcolombet at apple.com> wrote: > Hi Vivek, > > On Mar 16, 2016, at 1:00 PM, vivek pandya via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > Hello, > > Probably this may be too late to start thinking about this project but I > think this is particularly useful feature for LLVM. >

Hello everyone, As I mentioned in my previous posts,I am using a machinefunction pass to find all the loops in the program and do some analysis on them. I have completed my pass now and it works correctly. but the only issue is that,I have noticed that if I have two functions in my program, and one of them is part of the loop for another one ,by using runonmachinefunction(), I will get one loop

Hello, Probably this may be too late to start thinking about this project but I think this is particularly useful feature for LLVM. A quick use I can think of this is Implementing Inter-procedural Register Allocation ( for Research purpose ). I have start looking at the code for MachineFunctionPass, I think currently MachineModule class is not available ( the project work will include that ) but

Hello Ethan, > Hi Vivek, > > I've reviewed your MachineModulePass proposal and in general, I like > what I'm seeing. A few suggestions on how you can make it stronger: > > 1. Please go into more specific detail on your prior work with LLVM. > Specifically: > 1. Which optimizations and passes have you implemented in your > class assignments?

> On Jul 2, 2015, at 2:05 PM, Jim Grosbach <grosbach at apple.com> wrote: > >> >> On Jul 2, 2015, at 1:17 PM, Ethan J. Johnson <ejohns48 at cs.rochester.edu <mailto:ejohns48 at cs.rochester.edu>> wrote: >> >> Hi all, >> >> I am working on creating a MachineFunctionPass to perform an analysis on X86 code. After a bit of trouble, I was

Hi, I would like to learn the details regarding what exactly PGO does for basic block layout/code placement optimizations in llvm. Could you please point me to some descriptions? Is it close to this paper (Karl Pettis and Robert C. Hansen. 1990. Profile guided code positioning. PLDI'90) http://perso.ensta-paristech.fr/~bmonsuez/Cours/B6-4/Articles/papers15.pdf? Whether it is purely

> On May 15, 2016, at 12:43 AM, vivek pandya <vivekvpandya at gmail.com> wrote: > > > > Vivek Pandya > > > On Wed, May 11, 2016 at 9:43 AM, Mehdi Amini <mehdi.amini at apple.com <mailto:mehdi.amini at apple.com>> wrote: > >> On May 10, 2016, at 6:06 PM, Hal Finkel <hfinkel at anl.gov <mailto:hfinkel at anl.gov>> wrote: >>

> On May 10, 2016, at 6:06 PM, Hal Finkel <hfinkel at anl.gov> wrote: > > > > From: "vivek pandya" <vivekvpandya at gmail.com> > To: "llvm-dev" <llvm-dev at lists.llvm.org>, "Tim Amini Golling" <mehdi.amini at apple.com>, "Hal Finkel" <hfinkel at anl.gov> > Cc: "Quentin Colombet" <qcolombet

Yes there is also MachineRegisterInfo::UsedPhysRegMask which should be the union of all regmasks in the function. > On May 11, 2016, at 10:47 AM, Hal Finkel via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > > > From: "Matthias Braun" <matze at braunis.de> > To: "Hal Finkel" <hfinkel at anl.gov> > Cc: "vivek pandya"

----- Original Message ----- > From: "vivek pandya" <vivekvpandya at gmail.com> > To: "Matthias Braun" <matze at braunis.de> > Cc: "Hal Finkel" <hfinkel at anl.gov>, "llvm-dev" > <llvm-dev at lists.llvm.org> > Sent: Wednesday, May 11, 2016 1:14:07 PM > Subject: Re: [llvm-dev] [GSoC 2016] Interprocedural Register

Hi Craig, Thanks for the information. Can you point to the source that specifies tGPR to be R0 - R7? I tried to search in ARMInstrThumb.td but couldn’t find it. Thanks, - Jie On Apr 14, 2019, at 15:28, Craig Topper <craig.topper at gmail.com<mailto:craig.topper at gmail.com>> wrote: I believe there is probably a separate instruction in LLVM for thumb2 add. Probably starting with t2

*Vivek Pandya* On Wed, May 11, 2016 at 10:02 AM, vivek pandya <vivekvpandya at gmail.com> wrote: > > > *Vivek Pandya* > > > On Wed, May 11, 2016 at 9:43 AM, Mehdi Amini <mehdi.amini at apple.com> > wrote: > >> >> On May 10, 2016, at 6:06 PM, Hal Finkel <hfinkel at anl.gov> wrote: >> >> >> >>

*Vivek Pandya* On Wed, May 18, 2016 at 11:25 PM, Quentin Colombet <qcolombet at apple.com> wrote: > > On May 18, 2016, at 10:46 AM, vivek pandya <vivekvpandya at gmail.com> wrote: > > > > *Vivek Pandya* > > > On Wed, May 11, 2016 at 4:01 PM, Hal Finkel <hfinkel at anl.gov> wrote: > >> >> ------------------------------ >> >>

On 3/18/16 12:33 PM, Quentin Colombet via llvm-dev wrote: > Hi Vivek, > >> On Mar 16, 2016, at 1:00 PM, vivek pandya via llvm-dev >> <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: >> >> Hello, >> >> Probably this may be too late to start thinking about this project >> but I think this is particularly useful

*Vivek Pandya* On Wed, May 11, 2016 at 4:01 PM, Hal Finkel <hfinkel at anl.gov> wrote: > > ------------------------------ > > *From: *"vivek pandya" <vivekvpandya at gmail.com> > *To: *"Mehdi Amini" <mehdi.amini at apple.com> > *Cc: *"Hal Finkel" <hfinkel at anl.gov>, "Quentin Colombet" < > qcolombet at

Hello, I have written following code to check each register if it is used by machineFunction or not : MachineRegisterInfo *MRI = &MF.getRegInfo(); TargetRegisterInfo *TRI = (TargetRegisterInfo *)MF.getSubtarget().getRegisterInfo(); const TargetMachine &TM = MF.getTarget(); const MCRegisterInfo *MCRI = TM.getMCRegisterInfo(); DEBUG(dbgs() << "Function Name : " <<

> On May 11, 2016, at 3:31 AM, Hal Finkel via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > > From: "vivek pandya" <vivekvpandya at gmail.com> > To: "Mehdi Amini" <mehdi.amini at apple.com> > Cc: "Hal Finkel" <hfinkel at anl.gov>, "Quentin Colombet" <qcolombet at apple.com>, "llvm-dev"