similar to: Question about __builtin_assume()

I would like to propose that loop pragma `vectorize(disable)` actually means disabling the vectorizer for that loop. This perhaps sounds really obvious (I hope it does), but currently `vectorize(disable)` sets the vectorization width to 1, and that means the vectorizer will run and could perform other tricks such as interleaving. The main reason to change the behaviour is that it will be more what

Could we expose predicates defined in the target InstrInfo.td file to the MachineVerifier? We use BuildMI() to create many instructions after ISEL, but the predicates are not being checked at this point. Thus, I could forget to check the target and build an instruction that is illegal for a specific configuration. In such a case it would be nice if the MachineVerifier could detect this for me.

On Thu, Dec 20, 2018 at 11:17 AM Ido Schimmel <idosch at idosch.org> wrote: > > On Thu, Dec 20, 2018 at 03:09:22PM +0100, Christian Borntraeger wrote: > > On 20.12.2018 10:12, Ido Schimmel wrote: > > > +Willem > > > > > > On Thu, Dec 20, 2018 at 08:45:40AM +0100, Christian Borntraeger wrote: > > >> Folks, > > >> > >

On Thu, Dec 20, 2018 at 11:17 AM Ido Schimmel <idosch at idosch.org> wrote: > > On Thu, Dec 20, 2018 at 03:09:22PM +0100, Christian Borntraeger wrote: > > On 20.12.2018 10:12, Ido Schimmel wrote: > > > +Willem > > > > > > On Thu, Dec 20, 2018 at 08:45:40AM +0100, Christian Borntraeger wrote: > > >> Folks, > > >> > >

for (BasicBlock::reverse_iterator I = BB.rbegin(), E = BB.rend(); I != E; ) { Instruction& inst = *I; ++I; <-- iterator should be advanced to the previous instruction // Happens to be an Instruction::SExt. // Works fine if I iterate forwards if (isInstructionTriviallyDead(&inst, TLI)) inst.eraseFromParent(); } Sorry for the inexperienced question, but

On Fri, May 19, 2023 at 02:52:18PM -0700, Jakub Kicinski wrote: > On Fri, 19 May 2023 16:51:48 +0300 Ido Schimmel wrote: > > diff --git a/net/bridge/br_input.c b/net/bridge/br_input.c > > index fc17b9fd93e6..274e55455b15 100644 > > --- a/net/bridge/br_input.c > > +++ b/net/bridge/br_input.c > > @@ -46,6 +46,8 @@ static int br_pass_frame_up(struct sk_buff *skb) >

On Sun, Mar 26, 2023 at 05:41:06PM +0200, Hans Schultz wrote: > On Mon, Mar 20, 2023 at 10:44, Ido Schimmel <idosch at nvidia.com> wrote: > >> + $MZ $swp1 -c 1 -p 128 -t udp "sp=54321,dp=12345" \ > >> + -a $mac -b `mac_get $h2` -A 192.0.2.1 -B 192.0.2.2 -q > >> + tc_check_packets "dev $swp2 egress" 1 1 > >> + check_fail $?

On Tue, Mar 28, 2023 at 19:40, Ido Schimmel <idosch at nvidia.com> wrote: > On Sun, Mar 26, 2023 at 05:41:06PM +0200, Hans Schultz wrote: >> On Mon, Mar 20, 2023 at 10:44, Ido Schimmel <idosch at nvidia.com> wrote: >> >> + $MZ $swp1 -c 1 -p 128 -t udp "sp=54321,dp=12345" \ >> >> + -a $mac -b `mac_get $h2` -A 192.0.2.1 -B 192.0.2.2 -q >>

int %nlz10(uint %param.x) { %.t3 = shr uint %param.x, ubyte 1 ; <uint> [#uses=1] %.t4 = or uint %.t3, %param.x ; <uint> [#uses=2] %.t7 = shr uint %.t4, ubyte 2 ; <uint> [#uses=1] %.t8 = or uint %.t7, %.t4 ; <uint> [#uses=2] %.t11 = shr uint %.t8, ubyte 4 ; <uint> [#uses=1]

On Thu, May 18, 2023 at 07:08:47PM +0300, Nikolay Aleksandrov wrote: > On 18/05/2023 14:33, Ido Schimmel wrote: > > diff --git a/net/bridge/br_input.c b/net/bridge/br_input.c > > index fc17b9fd93e6..d8ab5890cbe6 100644 > > --- a/net/bridge/br_input.c > > +++ b/net/bridge/br_input.c > > @@ -334,6 +334,7 @@ static rx_handler_result_t br_handle_frame(struct sk_buff

Adjust drivers that support the 'FLOW_DISSECTOR_KEY_META' key to reject filters that try to match on the newly added layer 2 miss option. Add an extack message to clearly communicate the failure reason to user space. Example: # tc filter add dev swp1 egress pref 1 proto all flower skip_sw l2_miss true action drop Error: mlxsw_spectrum: Can't match on "l2_miss". We have

Does anyone have any good ideas to verify that the layout of a struct from the front end (field offsets and alignment) exactly match LLVM's interpretation of that struct? I want to support packing of structs and pragmas/attributes for alignment and validate that the front end and back end match. [ This is a different front end (ie. Not GNU based). ] For example: __packed struct S1 { char

Add MDB net device operations that will be invoked by rtnetlink code in response to received RTM_{NEW,DEL,GET}MDB messages. Subsequent patches will implement these operations in the bridge and VXLAN drivers. Signed-off-by: Ido Schimmel <idosch at nvidia.com> --- include/linux/netdevice.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/include/linux/netdevice.h

I found myself wanting a "scheduling barrier" in LLVM. In my specific circumstances I only want it to mean that TargetInstrInfoImpl::isSchedulingBoundary() would return true. I added SchedulingBarrier to MCID in MCInstrDesc.h and pushed it through TD attributes down to isSchedulingBoundary(). Is this something of general interest, or is there another mechanism for implementing

On Thu, Dec 20, 2018 at 9:16 AM Ido Schimmel <idosch at idosch.org> wrote: > > On Thu, Dec 20, 2018 at 09:04:25AM -0500, Willem de Bruijn wrote: > > On Thu, Dec 20, 2018 at 6:15 AM Ido Schimmel <idosch at idosch.org> wrote: > > > > > > +Willem > > > > > > On Thu, Dec 20, 2018 at 08:45:40AM +0100, Christian Borntraeger wrote: > >

I ran into a portability issue with drivers/bcmxcp.c in nut-2.4.1 on my UnixWare 7.1.4 machine. The error I get is ..... UX:acomp: ERROR: "/opt/src/utils/nut-2.4.1/drivers/bcmxcp.c", line 835: integral constant expression expected ..... Looking at the code we see ..... int init_outlet(unsigned char len) { unsigned char answer[len]; ..... Although gcc can handle it, it's not

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It would be really nice if llvm-as had some extra syntax to let other compilers specify the exact layout of a struct. Specifically, I'd like to specify what the byte offsets are for each field without having to insert phony fields. Would this extra functionality fit into your work at all? -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at

file://docs/LangRef.html#globalvars The section describing the definition of global vars discusses that you can specify an alignment and can also specify a section. Could someone provide an example that works in gccas in release 1.9 for both defining which section the var is assigned to and defining the variables alignment? Also, is there another document that describes how you define sections

Hello, Currently the loop vectorizer will, by default, not consider vectorization factors that would make it generate types that do not fit into the target platform's vector registers. That is, if the widest scalar type in the scalar loop is i64, and the platform's largest vector register is 256-bit wide, we will not consider a VF above 4. We have a command line option (-mllvm