similar to: VLIW support

Kun, Thanks for the reply. I looked at it, but wasn't able to find where actual instruction bundling takes place, i.e. where exactly in the code they pack instruction into a single bundle. Do you know where it is done? I would really appreciate any pointers. Thanks. On Fri, Sep 25, 2015 at 4:37 PM, Kun Ling <kunling at lingcc.com> wrote: > Hi Rail, > For the VLIW support,

Is there a way to convert between SchedMachineModel and Itineraries? I was trying to write a very simple VLIW packetizer (Hexagon was my starting point). It turns out that current DFAPacketizer is using itineraries, but my schedule is based on SchedMachineModel (I was recommended to use it since the itineraries are being phased out). I was wondering if there is an automated tool that would

Hello all, We're developing an integrated assembler for a VLIW target, and some of the optimizing our assembler needs to do must be done on a per-packet basis. This requires us to be able to traverse instruction within a packet, and one particular optimization requires traversal of previous packets as well. We're considering adding support for MCInst bundles in the MC layer to

> On Nov 9, 2015, at 10:49 AM, Rail Shafigulin <rail at esenciatech.com> wrote: > > On Mon, Nov 9, 2015 at 10:31 AM, Hal Finkel <hfinkel at anl.gov <mailto:hfinkel at anl.gov>> wrote: > ----- Original Message ----- > > From: "Rail Shafigulin via llvm-dev" <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> > > To:

----- Original Message ----- > From: "Rail Shafigulin via llvm-dev" <llvm-dev at lists.llvm.org> > To: "llvm-dev" <llvm-dev at lists.llvm.org> > Sent: Monday, November 9, 2015 10:09:07 AM > Subject: Re: [llvm-dev] Is there a way to convert between SchedMachineModel and Itineraries? > > > Anybody? Does anyone at all know how to do it? There is

Hi, I notice that there exist some classes for VLIW packetizing and other classes for VLIW scheduling. Apparently these classes share something in common. Can someone explain why they should have separate implementation (i.e., in different function passes)? Best regards. -- 杨勇勇 (Yang Yongyong)

I'm using a Hexagon's packetizer as an example to packetize instructions for my custom VLIW. The problem that I'm facing is that my target as it turns out doesn't have all the instructions expanded by the time packetization happens (for example I have a RET instruction which gets expanded into a write to a register and a jump/branch). I'm wondering if Hexagon is experiencing

I'm working on a custom VLIW (we call it Escala). At the moment I'm trying to implement EscalaAsmPrinter::EmitInstruction(const MachineInstr *MI). I'm trying to clone an instruction and this produces and error. Below are the code as well as error: void EscalaAsmPrinter::EmitInstruction(const MachineInstr *MI) { const MachineFunction *MF = MI->getParent()->getParent();

Hi Yang, They have different implementations because they don't do the same thing and don't rely on the same structures. VLIW scheduling works on the SelectionDAG, right after the instruction selection, and it will schedule the DAG but it will not build any packet. The VLIW packetizer has been designed to work with machine instructions, using the ScheduleDAGInstr, and it does build

On Aug 9, 2012, at 10:09 AM, Sergei Larin <slarin at codeaurora.org> wrote: > Yang, > > This might not be such a tough choice on engineering side - one of the > LLVM differentiators is the ground-up, early introduced support for VLIW > specific features… Actually, LLVM lacked support for VLIW until fairly recently, and it has relatively few VLIW-specific features. Dan

Hi, It seems the only one VLIW target Hexagon in LLVM 3.2 devel uses a straightforward way to emit its VLIW-style asm codes. It uses a list scheduler to schedule on DAG and a simple packetizer to wrap the emitted asm instructions. Both scheduling and packetizing work on basic blocks. so, is there any plan to implement better optimization methods such as trace scheduling, software pipelining, ...

Larin, Thank you for telling me about this. Our lab is planning to design a VLIW DSP and has to make a choice between GCC and LLVM, for which I take responsibility. As we all know that GCC's codes possess a long history and has a somewhat bad learning curve, I suggest choosing LLVM. It seems now the only drawback is its poor support for VLIW architecture. And so if we can count on

Has anyone attempted the port of LLVM to a VLIW architecture? Is there any publication about it? TIA -- Evandro Menezes Austin, TX emenezes at codeaurora.org Qualcomm Innovation Center, Inc is a member of Code Aurora Forum

Yang, There is work currently underway to add SW pipelining and some sort of global scheduling to Hexagon, but if there is some interest to it from other targets, it would be helpful to know. What is your involvement with this? Sergei Larin -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum. > -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu

But we are really striving to change it fast :) Dan, My comparative point was that LLVM has a greater potential to accommodate VLIW going forward than GCC does at this point. Would you agree to that? Sergei -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum. > -----Original Message----- > From: Dan Gohman [mailto:gohman at apple.com] > Sent: Friday, August 10,

Hi, > Has anyone attempted the port of LLVM to a VLIW architecture? Is there > any publication about it? I have developed a derivation of MachineInstr class, called MachineInstrBundle, which is essnetially a VLIW-style machine instruction which can store any MI on each "slot". After the scheduling phase has grouped MIs in bundles, it has to call MIB->pack() method, which

Hello, I want to implement vectorization and vliw(very long instruction word) in my specific dsp ,do you have any advices to me ? Thank you very much! -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20170220/7bfe1d15/attachment.html>

VLIW (Very Long Instruction Word) is a long instruction format (called "group" hereafter) contains several instructions. These instructions are not dependent on each other and could be issued in a single cycle. At this moment there is no correspondent class for VLIW. MachineInstr object can only represent one instruction. Usually the number of instructions in a group is fixed. The

hi guys I need to get llvm to support vliw architecture. Can you please point me in the right direction. we have managed to get it to compile into simple assemble and now need it to be able to schedule the instructions in parrallel. any help would be appreciated Regards Junior

Yang, This might not be such a tough choice on engineering side - one of the LLVM differentiators is the ground-up, early introduced support for VLIW specific features... As for the help offer - thanks... I'll definitely keep that in mind. The best help right now would be to keep on trying new VLIW related features as they got merged to LLVM tree and provide feedback... and we do plan to