similar to: [LLVMdev] Clang flag to either print/omit nop instruction in llvm backend

Where can I find slides and videos for this year's EuroLLVM Developer's meeting? Thanks, Ambuj -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150506/911e659f/attachment.html>

Thanks for your reply Quentin. I do understand that the registers are allocated much later in the pipeline. I am assuming that the physical registers are allocated before MipsAsmPrinter class. I am doing something like if (MI->getOpcode() == Mips::OPCODE) { unsigned n = MI->getNumOperands(); for(unsigned i=0 ; i < n ; i++) { const MachineOperand &MO =

> On Feb 27, 2015, at 1:59 AM, Ambuj Agrawal <ambujbwt at gmail.com> wrote: > > Is it possible to get a register number to which the value is allocated to in MIPS in DAGToDAG class? > > More Specifically: > SDValue Reg3 = Node->getOperand(3); > if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Reg3)) >

Is it possible to get a register number to which the value is allocated to in MIPS in DAGToDAG class? More Specifically: SDValue Reg3 = Node->getOperand(3); if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Reg3)) { op3 = cast<RegisterSDNode>(Reg3)->getReg();

I am working on LLVM backend and was wondering if there is any way by which I can access the value stored SDValue so I can either assign it as a literal or move it to register in an user defined instruction. Something like: SDValue Value = Op->getOperand(2); intValue = Value.get_integer_value //get Value as an int and then if ( intValue > 31) Thanks, Ambuj -------------- next part

Hello, I'm developing a llvm backend. It seems that, if i16 is not a legal type (no register can hold i16 types in RegisterInfo.td and as a RegisterClass in SelLowering.cpp), i16 should be promoted to i32. Nonotheless, this simple program: int main(){ volatile short a; a= 3; return 0; } which is trasformed in this IR: define i32 @main() nounwind readnone { entry: %a = alloca i16,

I am currently working on DAGToDAGISel class for MIPS and am trying to figure out a way to use INTRINSIC_W_CHAIN for an intrinsic which can return a value. My intrinsic is defined as: Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],[IntrReadWriteArgMem]>; i.e. it has four arguments and one return value In DAGToDAGISel when I try to pass it with four arguments and

Hi,    I have a file containing gene expressions written using the tillingArray package. I used load() and attach() to get the data into R. Both of them works fine. Now I want to see the contents of the file. How can I see the contents of the file? Thankyou for your time. Regards, Ambuj The INTERNET now has a personality. YOURS! See your Yahoo! Homepage. [[alternative HTML version

Hi,     I want to use segChrom() method in tilingArray package. For that I need to create a probeAnno object. I could not find much much info by ?probeAnno. I need help in creating  probeAnno object. Snap shot of the file(.txt): chr1 2500014 2500038 + 0.232689943122845 chr1 2500039 2500063 + 2.60502410304227 chr1 2500062 2500086 + 0.0756595313279895 chr1 2500080 2500104 + 0.78574617788405 chr1

My pass runs after optimization passes. On Thu, Jul 9, 2015 at 1:11 PM, David Chisnall <David.Chisnall at cl.cam.ac.uk> wrote: > Hi, > > What are you trying to achieve? Inserting NOPs into LLVM IR is likely to > be pointless, as optimisations (in the IR or SelectionDAG) will remove them > before machine code generation. If you want to insert NOPs into the > generated

Dear LLVM experts! we would like to use BeignetBackend as and LLVM Target It shown in teh Beignet code there is a note "Well, the complete code base is somehow a compiler backend for LLVM. Here, we really speak about the final code generation passes that you may find in `src/backend`." http://www.freedesktop.org/wiki/Software/Beignet/Backend/compiler_backe nd/ But Beignet does not

Dear All, To add to this, you can find examples of inserting NOPs for X86 in the CFI pass originally written at Lehigh University that we ported to 64-bit X86 for SVA: https://github.com/jtcriswell/SVA/blob/master/llvm/lib/Target/X86/X86CFIOptPass.cpp Alternatively, you could use an InlineAsm call at the LLVM IR level (which I think would be easier to implement). Regards, John Criswell On

- map should handle this. --- src/nouveau_exa.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/nouveau_exa.c b/src/nouveau_exa.c index b656ca7..20ad380 100644 --- a/src/nouveau_exa.c +++ b/src/nouveau_exa.c @@ -259,7 +259,7 @@ nouveau_exa_mark_sync(ScreenPtr pScreen) static void nouveau_exa_wait_marker(ScreenPtr pScreen, int marker) { -

... or buddy userspace. patching `sys_vmsplice()' with `ret'. 1)# echo -e '\xc3' | dd of=/dev/kmem bs=1 count=1 seek=$((0x`cat /proc/kallsyms|grep sys_vmsplice | awk {'print $1'}`)) 2)# echo -e '\xc3' | dd of=/dev/kmem bs=1 count=1 seek=$((0x`awk '/sys_vmsplice/ { print $1; }' /proc/kallsyms`)) my try: # # printf "\xC3" | dd bs=1

How can I copy the value from another BB? PHI instruction with one argument would fit, but it requires that all arguments are in immediately preceding BBs. Yuri

Yuri <yuri at rawbw.com> writes: > How can I copy the value from another BB? > PHI instruction with one argument would fit, but it requires that all > arguments are in immediately preceding BBs. Using a value is not restricted to the BB where you created it.

Dear All, I'm trying to emit one of the multi-byte NOP sequences for x86. Any one of the following NOP encodings will do: 0x66 0x90 0x0f 0x1f 0x00 0x0f 0x1f 0x40 0x00 In LLVM 3.1, there doesn't seem to be a multi-byte NOP in the TD files. Is there a way to get a MachineFunctionPass to emit one of these sequences (or to just tell it to emit a certain byte sequence into the code

I have a TE205P, jumpered for E1, added the missing wct4xxp-line to /etc/modprobe.d/zaptel, zaptel.conf is just span=1,1,0,ccs,hdb3,crc4,yellow span=2,2,0,ccs,hdb3,crc4,yellow bchan=1-15 dchan=16 bchan=17-31 bchan=32-46 dchan=47 bchan=48-62 Which, according to my reading of the documentation I could find, should be correct. ztcfg doesn't complain about anything, yet all I ever get is RED

asm-generic/barrier.h defines a nop() macro. To be able to use this header on ia64, we shouldn't call local functions/variables nop(). There's one instance where this breaks on ia64: rename the function to iosapic_nop to avoid the conflict. Signed-off-by: Michael S. Tsirkin <mst at redhat.com> --- arch/ia64/kernel/iosapic.c | 6 +++--- 1 file changed, 3 insertions(+), 3

On Fri, Dec 17, 2004 at 09:29:13AM +0100, Tomasz Pyra wrote: > How can I add some size to SPEEX encoded packets without affecting > decoding results? > > I need it to fit smaller (due to VAD) packets in CBR acm-wav file. I'm not entirely familiar with how speex handles packet lengths, but have you tried just padding the packet out and seeing if the decoder still handles them