similar to: [LLVMdev] Newbee question: LLVM backend regression tests for thumb1 targets on simulator possible?

On 12/16/14 3:53 AM, Kristof Beyls wrote: > I've been wondering too about how to get better ARM v6m compile-and-execute > testing going. > > As you say Jon, the non-execution-based regression tests are surprisingly > good at catching issues; but they're no full substitute for executing the > code produced by the backend for a reasonably-sized test suite. > > If

On 18 December 2014 at 04:02, Tim Northover <t.p.northover at gmail.com> wrote: >> You have some special version of qemu? My default distribution's qemu >> package did not have a cortex-M0 nor has qemu head freshly taken from git: > > The trouble with Cortex-M0 (from a virtualised testing perspective) is > that it doesn't have an MMU, so any "real"

> > $ qemu-arm -cpu ? > > Available CPUs: > > arm926 arm946 arm1026 arm1136 arm1136-r2 arm1176 arm11mpcore > > cortex-m3 > > cortex-a8 > > cortex-a8-r2 cortex-a9 cortex-a15 ti925t pxa250 sa1100 sa1110 > pxa255 pxa260 > > pxa261 pxa262 pxa270 pxa270-a0 pxa270-a1 pxa270-b0 pxa270-b1 xa270- > c0 > > pxa270-c5 any > > >

Hello, find enclosed a first patch for adding tail call optimizations for thumb1 targets. I assume that this list is the right place for publishing patches for review? Since this is my first proposal for LLVM, I'd very much appreciate your feedback. What the patch is meant to do: For Tail calls identified during DAG generation, the target address will be loaded into a register by use

Hello to all. When studying forums and mailing lists it seems to me that llvm usage for very small arm v6m targets is not so common. In the last months, I have spent some time on analyzing performance of llvm/clang for very small targets. My main objective was to get the best possible performance from portable (non-assembly) crypto numerics for cortex-M0(+) targets. As a result (crypto

Am 19.12.2014 11:00, schrieb Renato Golin: > On 18 December 2014 at 04:02, Tim Northover <t.p.northover at gmail.com> wrote: >>> You have some special version of qemu? My default distribution's qemu >>> package did not have a cortex-M0 nor has qemu head freshly taken from git: >> The trouble with Cortex-M0 (from a virtualised testing perspective) is >>

> > FWIW, I build baremetal newlib for arm-eabi using clang, and it works. I >> had to patch a few of the __attribute__((naked)) functions because they >> were using pre-UAL asm syntax, but for the most part it "just works". >> > I build the baremetal newlib using arm-none-eabi-gcc as well, but after linking with the hello world program, it failed to run on

Hi all, I think using code coverage on baremetal has come up once or twice on llvmdev, but I don't think anyone has actually written up how the workflow works, or what issues come up.  This description is based on work done together with my colleague Weiming Zhao. By "baremetal" here, I mean an embedded environment without an operating system.  We specifically used a ARM target

Jim/Tim/Renato, A few days ago (has it been weeks now?) we discussed a codegen problem on armv4t having to do with lo->lo register copies. I'd like to start that discussion again, this time with a patch. A brief summary of the problem for folks who didn't catch the discussion earlier, and those like me who forget what they ate for breakfast: ;] The mov instruction on armv4t

Bill Wendling <wendling at apple.com> writes: > Improving the test suite is always welcome. Do we have an idea of what sorts of improvements we'd like? Any codes that we want to add, for example? What would be useful for ARM? > In addition, we send out pre-release tarballs and have people in the > community build and test their programs with it. This is not a perfect >

Hi Raja, I'm open to suggestions. Our current release qualification is to bootstrap the compiler (similar to how GCC does their bootstrapping), run the test suites, and verify that there are no regressions. Improving the test suite is always welcome. In addition, we send out pre-release tarballs and have people in the community build and test their programs with it. This is not a perfect

Hi James, Thanks for the answer, can you elaborate on difference between thumb, thumb2, ARM, thumbv7. I'm a bit lost right now. When specifying thumbv7 llc will generate thumb only code, not thumb2 ? Best Regards Seb > -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > On Behalf Of James Molloy > Sent: Tuesday, May 29,

Hi Seb, The ARM instruction set is a fixed-width 32-bit instruction set that has been around since the early days of ARM. Modern (armv4t onwards) cores mostly have another instruction set that can be used in tandem, the "thumb" instruction set. This is a variable width (16 or 32 bit) instruction set that provides a subset of the ARM instruction set and was intended to provide the

Hello Sjoerd, Thank you for your response! I was not aware that -Oz is a closer equivalent to GCC's -Os. I tried -Oz when compiling with clang and confirmed that the Clang's generated assembly is equivalent to GCC for the code snippet I posted above. clang --target=armv6m-none-eabi -Oz -fomit-frame-pointer memcpy_alt1: push {r4, lr} movs r3, #0 .LBB0_1: cmp

Hi James, Thanks for the answer, for Cortex-A9 would you recommend to generate thumb2 code or ARM code ? What would be the best performance wise ? Best Regards Seb > -----Original Message----- > From: James Molloy [mailto:james.molloy at arm.com] > Sent: Thursday, May 31, 2012 9:57 AM > To: Sebastien DELDON-GNB > Cc: llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] llc support

Hi Everyone, is there the possibility in R to assign a variable to be an alias of another one? Example: x <- 17 # assign y to be an alias of x y # returns 17 x <- 4 y # returns 4 Daniel

Hi Eli, Thanks for your response. Actually, I look a lot at the ARM and THUMB1 backend implementations, and this certainly help. My architecture also have specific instructions for SP-relative accesses in a similar way than the Thumb1. During frame lowering, specific machine instructions are emitted so there’s no issue there. Also during ISelDagToDag I am able to select the right instructions.

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